RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 14 CAN CONTROLLER 14.6 Bit Set/Clear Function The CAN control registers include registers whose bits can be set or cleared via the CPU and via the CAN interface. An operation error occurs if the following registers are written directly. Do not write any values directly via bit manipulation, read/modify/write, or direct writing of target values. CAN global control register (C0GMCTRL, C1GMCTRL) CAN global automatic block transmission control register (C0GMABT, C1GMABT) CAN module control register (C0CTRL, C1CTRL) CAN module interrupt enable register (C0IE, C1IE) CAN module interrupt status register (C0INTS, C1INTS) CAN module receive history list register (C0RGPT, C1RGPT) CAN module transmit history list register (C0TGPT, C1TGPT) CAN module time stamp register (C0TS, C1TS) CAN message control register (C0MCTRLm, C1MCTRLm) Remark m = 0 to 15 All the 16 bits in the above registers can be read via the usual method. Use the procedure described in figure 14-23 below to set or clear the lower 8 bits in these registers. Setting or clearing of lower 8 bits in the above registers is performed in combination with the higher 8 bits (refer to the 16-bit data after a write operation in Figure 14-24). Figure 14-23 shows how the values of set bits or clear bits relate to set/clear/no change operations in the corresponding register. Register’s current values Write values Register’s value after write operations Figure 14-23. Example of Bit Setting/Clearing Operations 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 1 0 1 1 1 1 0 1 1 0 0 0 set 0 0 0 0 1 0 1 1 clear 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 R01UH0317EJ0004 Rev. 0.04 841 Feb. 22, 2013 Bit status Clear Clear No change Clear No change No change Set Set
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 14 CAN CONTROLLER Figure 14-24. 16-Bit Data during Write Operation 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 set 7 set 6 set 5 set 4 set 3 set 2 set 1 set 0 clear 7 clear 6 clear 5 clear 4 clear 3 clear 2 clear 1 clear 0 Remark n = 0 to 7 set n clear n Status of bit n after bit set/clear operation 0 0 No change 0 1 0 1 0 1 1 1 No change R01UH0317EJ0004 Rev. 0.04 842 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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14.9.1 Message reception ..........
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19.2 Configuration of DMA Controlle
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28.1.1 Programming Environment.....
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34.2 64-pin products 1276 R5F10CLDx
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RL78/D1A User’s Manual: Hardware
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