RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) LRxDn pin Internal successful BF flag Internal successful SF flag UFnHDC flag INTLSn INTLRn UFnBRS11 to UFnBRS00 bits “L” Figure 13-57. Example of Successful BF, SF, and PID Reception B Old value B ≥ C × 11 BF successful transmission/ reception disabled C 55H checked, based on C Transmission/ reception stopped 55H successful Baud rate setting transmission/ reception enabled Sets UFnCLHDC bit to 1 Clear R01UH0317EJ0004 Rev. 0.04 759 Feb. 22, 2013 PID New value Caution When a PID reception error has occurred, a status interrupt request signal (INTLSn) is generated instead of a reception complete interrupt request signal (INTLRn) and other error flags (such as UFnFE and UFnIPE) change. LRxDn pin INTLRn Figure 13-58. Example of Successful BF Reception During SF Reception (No PID Reception Error) Internal successful BF flag Internal successful SF flag UFnHDC flag INTLSn UFnBRS11 to UFnBRS00 bits B “L” B ≥ C × 11 BF successful transmission/ 55H failed reception disabled C D 55H checked, based on C Transmission/reception stopped Old value D ≥ E × 11 BF successful transmission/ reception disabled E 55H checked, based on E 55H successful Baud rate setting transmission/ reception enabled PID Sets UFnCLHDC bit to 1 Clear New value Caution When a PID reception error has occurred, a status interrupt request signal (INTLSn) is generated instead of a reception complete interrupt request signal (INTLRn) and other error flags (such as UFnFE and UFnIPE) change. Remark n = 0, 1
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) LRxDn pin INTLRn Figure 13-59. Example of Successful BF Reception During PID Reception (No PID2 Reception Error) Transmission/reception stopped Internal successful BF flag Internal successful SF flag UFnHDC flag INTLSn UFnBRS11 to UFnBRS00 bits 55H checked Old value 55H successful Baud rate setting transmission/ reception enabled PID1 Sets UFnCLHDC bit to 1 Stop bit position UFnFE = 1 D New value1 D ≥ E × 11 BF successful transmission/ reception disabled E 55H checked, based on E Clear Transmission/ reception stopped 55H successful Baud rate setting transmission/ reception enabled Sets UFnCLHDC bit to 1 Clear R01UH0317EJ0004 Rev. 0.04 760 Feb. 22, 2013 PID2 New value2 Caution If the PID1 stop bit position comes after the point where the internal successful BF flag has been set, the UFnHDC flag and error flags (such as UFnFE and UFnIPE) are not set, and INTLSn is also not generated. Figure 13-60. Example of Successful BF Reception During Data/CSF Reception (No PID Reception Error) LRxDn pin Internal successful BF flag Internal successful SF flag UFnHDC flag INTLSn INTLRn UFnBRS11 to UFnBRS00 bits Data/CSF Stop bit position UFnFE = 1 (UFnDCE = 1) Old value D D ≥ E × 11 BF successful transmission/ reception disabled E 55H checked, based on E Transmission/ reception stopped 55H successful Baud rate setting transmission/ reception enabled PID Sets UFnCLHDC bit to 1 Clear New value Caution If the Data/CSF stop bit position comes after the point where the internal successful BF flag has been set, the UFnBUC flag and error flags (such as UFnFE, UFnDCE, UFnCSE, and UFnRPE) are not set, and INTLSn is also not generated. Remark n = 0, 1
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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