RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 19 DMA CONTROLLER 19.2 Configuration of DMA Controller The DMA controller includes the following hardware. Table 19-1. Configuration of DMA Controller Item Configuration Address registers DMA SFR address registers 0 to 3 (DSA0 to DSA3) DMA RAM address registers 0 to 3 (DRA0 to DRA3) Count register DMA byte count registers 0 to 3 (DBC0 to DBC3) Control registers DMA mode control registers 0 to 3 (DMC0 to DMC3) DMA operation control register 0 to 3 (DRC0 to DRC3) DMA all-channel forced wait register (DWAITALL) Note. Channels 2 and 3 are only for 100-pin products. (1) DMA SFR address register n (DSAn) This is an 8-bit register that is used to set an SFR address that is the transfer source or destination of DMA channel n. Set the lower 8 bits of the SFR addresses FFF00H to FFFFFH. This register is not automatically incremented but fixed to a specific value. In the 16-bit transfer mode, the least significant bit is ignored and is treated as an even address. The DSAn register can be read or written in 8-bit units. However, it cannot be written during DMA transfer. Reset signal generation clears this register to 00H. Figure 19-1. Format of DMA SFR Address Register n (DSAn) Address: FFFB0H (DSA0), FFFB1H (DSA1), F0170H (DSA2), F0171H (DSA3) After reset: 00H R/W DSAn 7 6 5 4 3 2 1 0 Remark n: DMA channel number (n = 0 to 3) R01UH0317EJ0004 Rev. 0.04 1027 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 19 DMA CONTROLLER (2) DMA RAM address register n (DRAn) This is a 16-bit register that is used to set a RAM address that is the transfer source or destination of DMA channel n. Addresses of the internal RAM area other than the general-purpose registers can be set to this register. Set the lower 16 bits of the RAM address. This register is automatically incremented when DMA transfer has been started. It is incremented by +1 in the 8bit transfer mode and by +2 in the 16-bit transfer mode. DMA transfer is started from the address set to this DRAn register. When the data of the last address has been transferred, the DRAn register stops with the value of the last address +1 in the 8-bit transfer mode, and the last address +2 in the 16-bit transfer mode. In the 16-bit transfer mode, the least significant bit is ignored and is treated as an even address. The DRAn register can be read or written in 8-bit or 16-bit units. However, it cannot be written during DMA transfer. Reset signal generation clears this register to 0000H. Figure 19-2. Format of DMA RAM Address Register n (DRAn) Address: FFFB2H, FFFB3H (DRA0), FFFB4H, FFFB5H (DRA1) , After reset: 0000H R/W DRAn F0172H, F0173H (DRA2), F0174H, F0175H (DRA3) DRA0H: FFFB3H DRA1H: FFFB5H DRA2H: F0173H DRA3H: F0175H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Remark n: DMA channel number (n = 0 to 3) DRA0L: FFFB2H DRA1L: FFFB4H DRA2L: F0172H DRA3L: F0174H R01UH0317EJ0004 Rev. 0.04 1028 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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19.2 Configuration of DMA Controlle
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RL78/D1A User’s Manual: Hardware
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