RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
(6) LIN-UARTn option register 2 (UFnOPT2)
The UFnOPT2 register is an 8-bit register that controls serial communication operation of LIN-UARTn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Figure 13-6. Format of LIN-UARTn Option Register 2 (UFnOPT2)
Address: F0245H (UF0OPT2), F0265H (UF1OPT2) After reset: 00H R/W
7 6 5 4 3 2 1
UFnOPT2 0 0 0 0 0 0 UFnRXFL UFnITS
(n = 0, 1)
UFnRXFL Bit to select use of receive data noise filter
0 Uses noise filter.
1 Does not use noise filter.
The UFnRXFL bit is used to select use of the noise filter. See 13.9 Receive Data Noise Filter for
details.
Caution Be sure to set the UFnRXFL bit when UFnCTL0.UFnRXE is “0”.
UFnITS Transmission interrupt (INTLTn) generation timing select bit
0 Outputs transmission interrupt request upon transmission start.
1 Outputs transmission interrupt request upon transmission completion.
Caution Be sure to set the UFnITS bit when UFnCTL0.UFnTXE is “0”.
The UFnITS bit can be changed to 1 after transmission of the last data is started
only when completion of transmitting the last data must be known during
successive transmission (UFnITS = 0). However, the change must be completed
before the transmission is completed.
R01UH0317EJ0004 Rev. 0.04 694
Feb. 22, 2013