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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 14 CAN CONTROLLER<br />

(7) CAN module control register (C0CTRL, C1CTRL)<br />

The C0CTRL, C1CTRL register is used to control the operation mode of the CAN module.<br />

(a) Read<br />

(b) Write<br />

(a) Read<br />

Figure 14-31. Format of CAN Module Control Register (C0CTRL, C1CTRL) (1/4)<br />

Address: F05E0H (C0CTRL), F0390H (C1CTRL) After reset: 0000H R/W<br />

C0CTRL,<br />

C1CTRL<br />

C0CTRL,<br />

C1CTRL<br />

15 14 13 12 11 10 9 8<br />

0 0 0 0 0 0 RSTAT TSTAT<br />

7 6 5 4 3 2 1 0<br />

CCERC AL VALID PSMODE1 PSMODE0 OPMODE2 OPMODE1 OPMODE0<br />

15 14 13 12 11 10 9 8<br />

Set<br />

CCERC<br />

Set<br />

AL<br />

0 Set Set Set Set Set<br />

PSMODE1 PSMODE0 OPMODE2 OPMODE1 OPMODE0<br />

7 6 5 4 3 2 1 0<br />

Clear<br />

CCERC<br />

Clear<br />

AL<br />

Clear<br />

VALID<br />

RSTAT Reception Status Bit<br />

0 Reception is stopped.<br />

1 Reception is in progress.<br />

Clear Clear Clear Clear Clear<br />

PSMODE1 PSMODE0 OPMODE2 OPMODE1 OPMODE0<br />

Remark - The RSTAT bit is set to 1 under the following conditions (timing).<br />

- The SOF bit of a receive frame is detected<br />

- On occurrence of arbitration loss during a transmit frame<br />

- The RSTAT bit is cleared to 0 under the following conditions (timing)<br />

- When a recessive level is detected at the second bit of the interframe space<br />

- On transition to the initialization mode at the first bit of the interframe space<br />

R01UH0317EJ0004 Rev. 0.04 852<br />

Feb. 22, 2013

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