RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 14 CAN CONTROLLER
Reference: The CAN standard ISO 11898 specification defines the segments constituting the data bit time as shown in
Figure 14-19.
Figure 14-19. Reference: Configuration of Data Bit Time Defined by CAN Specification
Data bit time(DBT)
Sync segment Prop segment Phase segment 1 Phase segment 2
Sample point (SPT)
Segment Name Segment Length Description
Sync Segment
(Synchronization Segment)
Prop Segment Programmable to 1 to 8
or more
Phase Segment 1 Programmable to 1 to 8
Phase Segment 2 Phase Segment 1 or
IPT, whichever greater
SJW Programmable from
1TQ to length of
segment 1 or 4TQ,
whichever is smaller
Remark IPT : Information Processing Time
TQ : Time Quanta
R01UH0317EJ0004 Rev. 0.04 805
Feb. 22, 2013
SJW
1 This segment starts at the edge where the level changes
from recessive to dominant when hard-synchronization is
established.
This segment absorbs the delay of the output buffer, CAN
bus, and input buffer.
The length of this segment is set so that ACK is returned
before the start of phase segment 1.
Time of prop segment (Delay of output buffer) + 2 x
(Delay of CAN bus) + (Delay of input buffer)
This segment compensates for an error of data bit time.
The longer this segment, the wider the permissible range
but the slower the communication speed.
This width sets the upper limit of expansion or contraction
of the phase segment during resynchronization.