RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT
Table 12-2. Operating Clock Selection
SPSm Register Operation Clock (fMCK) Note
SMRmn
Register
CKSmn PRS PRS PRS PRS PRS PRS PRS PRS
fCLK = fCLK = fCLK = fCLK = fCLK =
m13 m12 m11 m10 m03 m02 m01 m00
4 MHz 8 MHz 16 MHz 24 MHz 32 MHz
0 X X X X 0 0 0 0 fCLK 4 MHz 8 MHz 16 MHz 24 MHz 32 MHz
1
X X X X 0 0 0 1 fCLK/2 2 MHz 4 MHz 8 MHz 12 MHz 16 MHz
X X X X 0 0 1 0 fCLK/2 2
1 MHz 2 MHz 4 MHz 6 MHz 8 MHz
X X X X 0 0 1 1 fCLK/2 3
500 kHz 1 MHz 2 MHz 3 MHz 4 MHz
X X X X 0 1 0 0 fCLK/2 4
250 kHz 500 kHz 1 MHz 1.5 MHz 2 MHz
X X X X 0 1 0 1 fCLK/2 5
125 kHz 250 kHz 500 kHz 750 kHz 1 MHz
X X X X 0 1 1 0 fCLK/2 6
62.5 kHz 125kHz 250 kHz 375 kHz 500 kHz
X X X X 0 1 1 1 fCLK/2 7
31.25 kHz 62.5 kHz 125 kHz 187.5kHz 250 kHz
X X X X 1 0 0 0 fCLK/2 8
15.625 kHz 31.25 kHz 62.5 kHz 93.75kHz 125 kHz
X X X X 1 0 0 1 fCLK/2 9
7.8125 kHz 15.625 kHz 31.25 kHz 46.86 kHz 62.5 kHz
X X X X 1 0 1 0 fCLK/2 1
0
3.90625 kHz 7.8125 kHz 15.625 kHz 23.44 kHz 31.25 kHz
X X X X 1 0 1 1 fCLK/2 1
1
1.953125 kHz 3.90625 kHz 7.8125 kHz 11.72 kHz 15.625 kHz
X X X X 1 1 1 1 INTTM23
0 0 0 0 X X X X fCLK 4 MHz 8 MHz 16 MHz 24 MHz 32 MHz
0 0 0 1 X X X X fCLK/2 2 MHz 4 MHz 8 MHz 12 MHz 16 MHz
0 0 1 0 X X X X fCLK/2 2
1 MHz 2 MHz 4 MHz 6 MHz 8 MHz
0 0 1 1 X X X X fCLK/2 3
500 kHz 1 MHz 2 MHz 3 MHz 4 MHz
0 1 0 0 X X X X fCLK/2 4
250 kHz 500 kHz 1 MHz 1.5 MHz 2 MHz
0 1 0 1 X X X X fCLK/2 5
125 kHz 250 kHz 500 kHz 750 kHz 1 MHz
0 1 1 0 X X X X fCLK/2 6
62.5 kHz 125kHz 250 kHz 375 kHz 500 kHz
0 1 1 1 X X X X fCLK/2 7
31.25 kHz 62.5 kHz 125 kHz 187.5kHz 250 kHz
1 0 0 0 X X X X fCLK/2 8
15.625 kHz 31.25 kHz 62.5 kHz 93.75kHz 125 kHz
1 0 0 1 X X X X fCLK/2 9
7.8125 kHz 15.625 kHz 31.25 kHz 46.86 kHz 62.5 kHz
1 0 1 0 X X X X fCLK/2 1
0
3.90625 kHz 7.8125 kHz 15.625 kHz 23.44 kHz 31.25 kHz
1 0 1 1 X X X X fCLK/2 1
1
1 1 1 1 X X X X INTTM23
Other than above Setting prohibited
1.953125 kHz 3.90625 kHz 7.8125 kHz 11.72 kHz 15.625 kHz
Note When changing the clock selected for fCLK (by changing the system clock control register (CKC) value),
do so after having stopped (STm = 0003H) the operation of the serial array unit m (SAUm). When
selecting INTTM23 for the operation clock, also stop the timer array unit 2 (TAU2) (TT2 = 00FFH).
Remarks 1. X: Don’t care
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 1)
R01UH0317EJ0004 Rev. 0.04 647
Feb. 22, 2013