RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 24 VOLTAGE DETECTOR Supply voltage (VDD) Figure 24-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 0) (2/2) When a condition of VDD is VDD < VLVIH after releasing the mask, a reset is generated because ofLVIMD = 1 (reset mode). VLVDH VLVDL LVIMK flag (set by software) Operation status LVIF flag LVISEN flag (set by software) LVIOMSK flag LVIMD flag LVILV flag LVIRF flag LVD reset signal POR reset signal Internal reset signal INTLVI LVIIF flag RESET Note 1 H Cleared by software Normal operation Cleared by software Save processing RESET Normal operation RESET Cleared by software Note 2 (Notes and Remark are listed on the next page.) Save processing Cleared by software Note 3 R01UH0317EJ0004 Rev. 0.04 1127 Feb. 22, 2013 W Time Cleared Cleared Note 3
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 24 VOLTAGE DETECTOR Notes 1. The LVIMK flag is set to “1” by reset signal generation. 2. After an interrupt is generated, perform the processing according to Figure 24-7 Processing Procedure After an Interrupt Is Generated in interrupt and reset mode. 3. After a reset is released, perform the processing according to Figure 24-8 Initial Setting of Interrupt and Reset Mode in interrupt and reset mode. Remark VPOR: POR power supply rise detection voltage VPDR: POR power supply fall detection voltage R01UH0317EJ0004 Rev. 0.04 1128 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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RL78/D1A User’s Manual: Hardware
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RL78/D1A User's Manual: Hardware - Renesas

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