RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 18 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Note The DIVST bit can only be set (1) in the division mode. In the division mode, division operation is started by setting (1) the DIVST bit. The DIVST bit is automatically cleared (0) when the operation ends. In the multiplication mode, operation is automatically started by setting the multiplier and multiplicand to multiplication/division data register A (MDAH, MDAL), respectively. Cautions 1. Do not rewrite the DIVMODE, MDSM bits during operation processing (while the DIVST bit is 1). If it is rewritten, the operation result will be an undefined value. 2. The DIVST bit cannot be cleared (0) by using software during division operation processing (while the DIVST bit is 1). R01UH0317EJ0004 Rev. 0.04 1017 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 18 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 18.4 Operations of Multiplier and Divider/Multiply-Accumulator 18.4.1 Multiplication (unsigned) operation • Initial setting Set the multiplication/division control register (MDUC) to 00H. Set the multiplicand to multiplication/division data register A (L) (MDAL). Set the multiplier to multiplication/division data register A (H) (MDAH). (There is no preference in the order of executing steps and . Multiplication operation is automatically started when the multiplier and multiplicand are set to the MDAH and MDAL registers, respectively.) • During operation processing Wait for at least one clock. The operation will end when one clock has been issued. • Operation end Read the product (lower 16 bits) from multiplication/division data register B (L) (MDBL). Read the product (higher 16 bits) from multiplication/division data register B (H) (MDBH). (There is no preference in the order of executing steps and .) • Next operation The next time multiplication, division or multiply-accumulation is performed, start with the initial settings of each step. Remark Steps to correspond to to in Figure 18-6. Figure 18-6. Timing Diagram of Multiplication (Unsigned) Operation (2 3 = 6) R01UH0317EJ0004 Rev. 0.04 1018 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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RL78/D1A User’s Manual: Hardware
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