RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 11 A/D CONVERTER Cautions 1. If using the hardware trigger wait mode, setting the ADCS bit to 1 is prohibited (but the bit is automatically switched to 1 when the hardware trigger signal is detected). However, it is possible to clear the ADCS bit to 0 to specify the A/D conversion standby status. 2. While in the one-shot conversion mode of the hardware trigger no-wait mode, the ADCS flag is not automatically cleared to 0 when A/D conversion ends. Instead, 1 is retained. 3 Only rewrite the value of the ADCE bit when ADCS = 0 (while in the conversion stopped/conversion standby status). 4 To complete A/D conversion, specify at least the following time as the hardware trigger interval: Hardware trigger no wait mode: 2 fCLK clock + A/D conversion time Hardware trigger wait mode: 2 fCLK clock + stabilization wait time + A/D conversion time Remark fCLK: CPU/peripheral hardware clock frequency R01UH0317EJ0004 Rev. 0.04 513 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 11 A/D CONVERTER Table 11-3. A/D Conversion Time Selection (1/4) (1) When there is no stabilization wait time Normal mode 1, 2 (software trigger mode/hardware trigger no-wait mode) A/D Converter Mode Mode Conversion Number of Number of Stabilization Stabilization Wait + Conversion Time Selection Register 0 (ADM0) Clock (fAD) Stabilization Conversion Wait 2.7 V VDD 5.5 V FR2 FR1 FR0 LV1 LV0 Wait Cock Clock +Conversion fCLK = fCLK = fCLK = fCLK = fCLK = Time 1 MHz 4 MHz 8 MHz 16 MHz 32 MHz 0 0 0 0 0 Normal fCLK/64 - 19 fAD 1216/fCLK Setting Setting Setting Setting 38 s 1 (number of prohibited prohibited prohibited prohibited 0 0 1 fCLK/32 sampling 608/fCLK 38 s 19 s 0 1 0 fCLK/16 clock: 304/fCLK 38 s 19 s 9.5 s 0 1 1 fCLK/8 7 fAD) 152/fCLK 38 s 19 s 9.5 s 4.75 s 1 0 0 fCLK/6 114/fCLK 28.5 s 14.25 s 7.125 s 3.5625 s 1 0 1 fCLK/5 95/fCLK 23.75 s 11.875 s 5.938 s 2.9688 s 1 1 0 fCLK/4 76/fCLK R01UH0317EJ0004 Rev. 0.04 514 Feb. 22, 2013 Note 19 s 9.5 s 4.75 s 2.375 s 1 1 1 fCLK/2 38/fCLK 38 s 9.5 s 4.75 s 2.375 s Setting Note prohibited 0 0 0 0 1 Normal fCLK/64 - 17 fAD 1088/fCLK Setting Setting Setting Setting 34 s 2 (number of prohibited prohibited prohibited prohibited 0 0 1 fCLK/32 sampling 544/fCLK 34 s 17 s 0 1 0 fCLK/16 clock: 272/fCLK 34 s 17 s 8.5 s 0 1 1 fCLK/8 5 fAD) 136/fCLK 34 s 17 s 8.5 s 4.25 s 1 0 0 fCLK/6 102/fCLK 25.5 s 12.75 s 6.375 s 3.1875 s 1 0 1 fCLK/5 85/fCLK 21.25 s 10.625 s 5.3125 s 2.6563 s 1 1 0 fCLK/4 68/fCLK 1 1 1 fCLK/2 Note Setting prohibited when VDD < 3.6 V Note Note 17 s 8.5 s 4.25 s 2.125 s 34/fCLK 34 s 8.5 s 4.25 s 2.125 s Note Note Setting prohibited Cautions 1. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the same data, while in the conversion stopped/conversion standby status (ADCS = 0). 2. The above conversion time does not include conversion start time. Conversion start time add in the first conversion. Select conversion time, taking clock frequency errors into consideration. Remark fCLK: CPU/peripheral hardware clock frequency
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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34.2 64-pin products 1276 R5F10CLDx
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RL78/D1A User’s Manual: Hardware
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