RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT
(Essential)
(Selective)
(Selective)
(Selective)
(Selective)
(Selective)
(Selective)
(Essential)
(Essential)
(Essential)
Figure 12-37. Procedure for Resuming Master Reception
Starting setting for resumption
Port manipulation
Changing setting of SPSm register
Changing setting of SDRmn register
Changing setting of SMRmn register
Changing setting of SCRmn register
Changing setting of SOm register
Clearing error flag
Port manipulation
Writing to SSm register
Starting communication
Disable clock output of the target
channel by setting a port register and a
port mode register.
Change the setting if an incorrect division
ratio of the operation clock is set.
Change the setting if an incorrect
transfer baud rate is set.
Change the setting if the setting of the
SMRmn register is incorrect.
Change the setting if the setting of the
SCRmn register is incorrect.
Manipulate the CKOmn bit and set a
clock output level.
Cleared by using SIRmn register if FEF,
PEF, or OVF flag remains set.
Enable clock output of the target channel
by setting a port register and a port mode
register.
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
Set dummy data to the SDRmn register
and start communication.
R01UH0317EJ0004 Rev. 0.04 605
Feb. 22, 2013