RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) (8) LIN-UARTn status clear register (UFnSTC) The UFnSTC register is a 16-bit register that is used to clear an LIN-UARTn status flag. This register can be read and written, in 16-bit units. Reset sets this register to 0000H. Caution An LIN-UART status register (UFnSTR) flag can be cleared by writing “1” to a corresponding bit. 0 will be read if the bit is read. Figure 13-8. Format of LIN-UARTn Status Clear Register (UFnSTC) (1/2) Address: F0248H, F0249H (UF0STC), F0268H, F0269H (UF1STC) After reset: 0000H R/W 15 14 13 12 11 10 9 8 UFnSTC 0 UFnCLIPE UFnCLCSE UFnCLRPE UFnCLHDC UFnCLBUC UFnCLIDM UFnCLEBD (n = 0, 1) 7 6 5 4 3 2 1 0 0 0 0 UFnCLBSF UFnCLDCE UFnCLPE UFnCLFE UFnCLOVE UFnCLIPE Channel n ID parity error flag clear trigger 0 Trigger does not operate. 1 Clears (0) the UFnIPE bit of the UFnSTR register. UFnCLCSE Channel n checksum error flag clear trigger 0 Trigger does not operate. 1 Clears (0) the UFnCSE bit of the UFnSTR register. UFnCLRPE Channel n response preparation error flag clear trigger 0 Trigger does not operate. 1 Clears (0) the UFnRPE bit of the UFnSTR register. UFnCLHDC Channel n header reception completion flag clear trigger 0 Trigger does not operate. 1 Clears (0) the UFnHDC bit of the UFnSTR register. UFnCLBUC Channel n buffer transmission/reception completion flag clear trigger 0 Trigger does not operate. 1 Clears (0) the UFnBUC bit of the UFnSTR register. UFnCLIDM Channel n ID match flag clear trigger 0 Trigger does not operate. 1 Clears (0) the UFnIDM bit of the UFnSTR register. UFnCLEBD Channel n expansion bit detection flag clear trigger 0 Trigger does not operate. 1 Clears (0) the UFnEBD bit of the UFnSTR register. R01UH0317EJ0004 Rev. 0.04 701 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) Figure 13-8. Format of LIN-UARTn Status Clear Register (UFnSTC) (2/2) UFnCLBSF Channel n successful BF reception flag clear trigger 0 Trigger does not operate. 1 Clears (0) the UFnBSF bit of the UFnSTR register. UFnCLDCE Channel n data consistency error flag clear trigger 0 Trigger does not operate. 1 Clears (0) the UFnDCE bit of the UFnSTR register. UFnCLPE Channel n parity error flag clear trigger 0 Trigger does not operate. 1 Clears (0) the UFnPE bit of the UFnSTR register. UFnCLFE Channel n framing error flag clear trigger 0 Trigger does not operate. 1 Clears (0) the UFnFE bit of the UFnSTR register. UFnCLOVE Channel n overrun error flag clear trigger 0 Trigger does not operate. 1 Clears (0) the UFnOVE bit of the UFnSTR register. R01UH0317EJ0004 Rev. 0.04 702 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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34.2 64-pin products 1276 R5F10CLDx
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RL78/D1A User’s Manual: Hardware
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