RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 11 A/D CONVERTER The ANI0/P20 to ANI7/P27 pins are as shown below depending on the settings of the A/D port configuration register (ADPC), analog input channel specification register (ADS), and PM2 registers. Table 11-4. Setting Functions of ANI0/P20 to ANI7/P27 Pins ADPC PM2 ADS ANI0/P20 to ANI7/P27 Pins Digital I/O selection Analog input selection Input mode Digital input Output mode Digital output Input mode Output mode Selects ANI. Analog input (to be converted) Does not select ANI. Analog input (not to be converted) Selects ANI. Does not select ANI. Setting prohibited The ANI18/P150 pin is as shown below depending on the settings of the A/D port configuration register (ADPC), analog input channel specification register (ADS), and PM15 registers. Table 11-5. Setting Functions of ANI8/P150 Pins ADPC PM15 ADS ANI8/P150 Pins Digital I/O selection Analog input selection Input mode Digital input Output mode Digital output Input mode Output mode Selects ANI. Analog input (to be converted) Does not select ANI. Analog input (not to be converted) Selects ANI. Does not select ANI. Setting prohibited R01UH0317EJ0004 Rev. 0.04 527 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 11 A/D CONVERTER 11.4 A/D Converter Conversion Operations The A/D converter conversion operations are described below. The voltage input to the selected analog input channel is sampled by the sample & hold circuit. When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the sampled voltage is held until the A/D conversion operation has ended. Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to (1/2) AVREF by the tap selector. The voltage difference between the series resistor string voltage tap and sampled voltage is compared by the voltage comparator. If the analog input is greater than (1/2) AVREF, the MSB bit of the SAR register remains set to 1. If the analog input is smaller than (1/2) AVREF, the MSB bit is reset to 0. Next, bit 8 of the SAR register is automatically set to 1, and the operation proceeds to the next comparison. The series resistor string voltage tap is selected according to the preset value of bit 9, as described below. Bit 9 = 1: (3/4) AVREF Bit 9 = 0: (1/4) AVREF The voltage tap and sampled voltage are compared and bit 8 of the SAR register is manipulated as follows. Sampled voltage Voltage tap: Bit 8 = 1 Sampled voltage < Voltage tap: Bit 8 = 0 Comparison is continued in this way up to bit 0 of the SAR register. Upon completion of the comparison of 10 bits, an effective digital result value remains in the SAR register, and the result value is transferred to the A/D conversion result register (ADCR, ADCRH) and then latched. At the same time, the A/D conversion end interrupt request (INTAD) can also be generated. Repeat steps to , until the ADCS bit is cleared to 0 Note2 . To stop the A/D converter, clear the ADCS bit to 0. Notes 1. If the A/D conversion result is outside the A/D conversion result range specified by the ADRCK bit and the ADUL and ADLL registers (see Figure 11-8), the A/D conversion result interrupt request signal is not generated and no A/D conversion results are stored in the ADCR and ADCRH registers. 2. While in the sequential conversion mode, the ADCS flag is not automatically cleared to 0. This flag is not automatically cleared to 0 while in the one-shot conversion mode of the hardware trigger no-wait mode, either. Instead, 1 is retained. Remarks 1. Two types of the A/D conversion result registers are available. ADCR register (16 bits): Store 10-bit A/D conversion value ADCRH register (8 bits): Store 8-bit A/D conversion value 2. AVREF: The + side reference voltage of the A/D converter. This can be selected from AVREFP, the internal reference voltage (1.45 V), and VDD. R01UH0317EJ0004 Rev. 0.04 528 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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RL78/D1A User’s Manual: Hardware
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