RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 22 RESET FUNCTION Figure 22-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) CLM reset control register (RESFCLM) LVIRF RPERF IAWRF WDTRF TRAP CLKRF Set Set Set Set Set Set Watchdog timer reset signal Clock monitor reset signal Clear Clear Clear Clear Clear Reset signal by execution of illegal instruction Reset signal by RAM parity error Reset signal by illegal-memory access RESFCLM register read signal RESF register read signal Reset signal to LVIM/LVIS register RESET R01UH0317EJ0004 Rev. 0.04 1093 Feb. 22, 2013 Power-on reset circuit reset signal Reset signal Voltage detector reset signal POCRES0 POC reset confirm register (POCRES) Caution An LVD circuit internal reset does not reset the LVD circuit. Remarks 1. LVIM: Voltage detection register 2. LVIS: Voltage detection level register
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 22 RESET FUNCTION High-speed on-chip oscillator clock High-speed system clock (when X1 oscillation is selected) CPU status RESET Internal reset signal Port pin (except P130) Note 1 Port pin (P130) Normal operation Figure 22-2. Timing of Reset by RESET Input Delay Reset period Wait for oscillation accuracy stabilization Normal operation (High-speed on-chip oscillator clock) R01UH0317EJ0004 Rev. 0.04 1094 Feb. 22, 2013 Note 2 Starting X1 oscillation is specified by software. Reset processing : 388 to 673 μs (When LVD is used) 156 to 360 μs (When LVD off) Figure 22-3. Timing of Reset Due to Execution of Illegal Instruction or Watchdog Timer Overflow High-speed on-chip oscillator clock High-speed system clock (when X1 oscillation is selected) CPU status Execution of Illegal Instruction/ Watchdog timer overflow Internal reset signal Port pin (except P130) Note 1 Port pin (P130) Normal operation Reset period (oscillation stop) Wait for oscillation accuracy stabilization Reset processing 41 to 69 μs Note 2 Hi-Z Starting X1 oscillation is specified by software. Normal operation (High-speed on-chip oscillator clock) Notes 1. Segment output pin is pull-downed while POR reset or RESET input is stay active. 2. When P130 is set to high-level output before reset is effected, the output signal of P130 can be dummyoutput as a reset signal to an external device, because P130 outputs a low level when reset is effected. To release a reset signal to an external device, set P130 to high-level output by software. Caution A watchdog timer internal reset resets the watchdog timer. Hi-Z
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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19.2 Configuration of DMA Controlle
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28.1.1 Programming Environment.....
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