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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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<br />

Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 11 A/D CONVERTER<br />

11.6 A/D Converter Operation Modes<br />

The operation of each A/D converter mode is described below. In addition, the procedure for specifying each mode is<br />

described in 11.7 A/D Converter Setup Flowchart.<br />

11.6.1 Software trigger mode (select mode, sequential conversion mode)<br />

In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the<br />

A/D conversion standby status.<br />

After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to<br />

perform the A/D conversion of the analog input specified by the analog input channel specification register (ADS).<br />

When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH),<br />

and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion ends, the next<br />

A/D conversion immediately starts.<br />

When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and<br />

conversion restarts. The partially converted data is discarded.<br />

When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D<br />

conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register.<br />

The partially converted data is discarded.<br />

Even if a hardware trigger is input during conversion operation, A/D conversion does not start.<br />

When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the<br />

system enters the A/D conversion standby status.<br />

When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status.<br />

When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start.<br />

Figure 11-19. Example of Software Trigger Mode (Select Mode, Sequential Conversion Mode) Operation Timing<br />

ADCE<br />

The trigger<br />

is not<br />

acknowledged.<br />

ADCS<br />

ADS<br />

A/D<br />

conversion<br />

status<br />

ADCR,<br />

ADCRH<br />

INTAD<br />

Stop<br />

status<br />

ADCE is set to 1.<br />

ADCE is cleared to 0. <br />

Conversion<br />

standby<br />

ADCS is set to 1 while in the<br />

conversion standby status.<br />

Data 0<br />

ADS is rewritten during<br />

A/D conversion operation<br />

(from ANI0 to ANI1).<br />

Data 1<br />

(ANI0)<br />

(ANI1)<br />

A/D conversion <br />

ends and the next<br />

conversion starts.<br />

Conversion is <br />

interrupted<br />

and restarts.<br />

<br />

Data 0<br />

(ANI0)<br />

Data 0<br />

(ANI0)<br />

Data 0<br />

(ANI0)<br />

Data 0<br />

(ANI0)<br />

Data 0<br />

(ANI0)<br />

Data 1<br />

(ANI1)<br />

Data 1<br />

(ANI1)<br />

Data 0<br />

(ANI0)<br />

ADCS is overwritten<br />

<br />

with 1 during A/D<br />

conversion operation.<br />

Data 0<br />

(ANI0)<br />

A hardware trigger<br />

<br />

is generated<br />

(and ignored).<br />

R01UH0317EJ0004 Rev. 0.04 531<br />

Feb. 22, 2013<br />

Data 0<br />

(ANI0)<br />

ADCS is cleared to<br />

<br />

0 during A/D<br />

conversion operation.<br />

Data 1<br />

(ANI1)<br />

<br />

Data 1<br />

(ANI1)<br />

Conversion is<br />

interrupted.<br />

Conversion<br />

standby<br />

Data 1<br />

(ANI1)<br />

The trigger<br />

is not<br />

acknowledged.<br />

Stop<br />

status

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