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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)<br />

Therefore, the maximum baud rate that can be received by the destination is as follows.<br />

BRmax = (FLmin/11) 1 22k<br />

= Brate<br />

21k + 2<br />

Similarly, obtaining the following maximum allowable transfer rate yields the following.<br />

10<br />

k + 2 21k 2<br />

FLmax = 11 FL FL = FL<br />

11<br />

2 k 2 k<br />

21k 2<br />

FLmax = FL 11<br />

20 k<br />

Therefore, the minimum baud rate that can be received by the destination is as follows.<br />

BRmin = (FLmax/11) 1 20k<br />

= Brate<br />

21k 2<br />

Table 13-10 shows the allowable baud rate error for UARTn and the destination calculated from the above-described<br />

equations for obtaining the minimum and maximum baud rate values.<br />

Division Ratio (k)<br />

Table 13-10. Maximum/Minimum Allowable Baud Rate Error<br />

Maximum Allowable Baud Rate Error Minimum Allowable Baud Rate Error<br />

BN = 9 BN = 11 BN = 12 BN = 9 BN = 11 BN = 12<br />

4 +2.85% +2.32% +2.12% 3.03% 2.43% 2.22%<br />

8 +4.34% +3.52% +3.22% 4.47% 3.61% 3.29%<br />

20 +5.10% +4.14% +3.78% 5.18% 4.19% 3.82%<br />

50 +5.68% +4.60% +4.20% 5.70% 4.61% 4.21%<br />

100 +5.78% +4.68% +4.27% 5.79% 4.69% 4.28%<br />

256 +5.83% +4.72% +4.31% 5.83% 4.72% 4.31%<br />

512 +5.85% +4.74% +4.33% 5.86% 4.74% 4.33%<br />

1024 +5.87% +4.75% +4.33% 5.87% 4.75% 4.33%<br />

2048 +5.87% +4.75% +4.34% 5.87% 4.75% 4.34%<br />

4095 +3.42% +4.75% +4.34% 3.59% 4.75% 4.34%<br />

Remarks 1. The reception accuracy depends on the bit count in 1 frame, the input clock frequency, and the division<br />

ratio (k). The higher the input clock frequency and the larger the division ratio (k), the higher the<br />

accuracy.<br />

2. BN: Number of bits from the start bit to the stop bit<br />

K: Setting values of UFnCTL1.UFnBRS[11:0]<br />

R01UH0317EJ0004 Rev. 0.04 781<br />

Feb. 22, 2013

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