RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) Figure 13-21. Format of LIN-UART Transmit/Receive Data (2/2) (e) 7-bit data length, MSB first, odd parity, 2 stop bits, transfer data: 36H Start bit 1 data frame D7 D6 D5 D4 D3 D2 D1 Parity bit (f) 8-bit data length, LSB first, no parity, 1 stop bit, transfer data: 87H Start bit 1 data frame D0 D1 D2 D3 D4 D5 D6 D7 (g) 8-bit data length, LSB first, even parity, expansion bit: enabled, 1 stop bit, transfer data: 155H Start bit 1 data frame D0 D1 D2 D3 D4 D5 D6 D7 R01UH0317EJ0004 Rev. 0.04 719 Feb. 22, 2013 Stop bit Stop bit Stop bit Expansion Parity Stop bit bit bit (h) 8-bit data length, MSB first, even parity, expansion bit: enabled, 1 stop bit, transfer data: 155H Start bit Expansion bit 1 data frame D7 D6 D5 D4 D3 D2 D1 D0 Parity bit Stop bit
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) 13.5.2 Data transmission Figure 13-22 shows the procedure for transmitting data. Figure 13-22. Transmission Processing Flow START Baud rate setting (UFnCTL1 register) Transmit data level setting (UFnOPT0 register) Various mode settings (UFnOPT1 register) INTLTn timing setting (UFnOPT2 register) Various mode settings, enabling transmission (UFnCTL0 register) Write UFnTX register INTLTn signal generated? END Yes All transmit data written? Yes Cautions 1. When initializing (UFnTXE = 0) the transmission unit, be sure to confirm that the transmission status flag has been reset (UFnTSF = 0). When initialization is performed while UFnTSF is “1”, transmission is aborted midway. 2. During LIN communication, confirm that a status interrupt request signal (INTLSn) has been generated, because reception is performed simultaneously with transmission. 3. When data consistency error detection has been set (UFnDCS = 1) and a data consistency error has been detected during LIN communication, transmission of the next data frame or BF is stopped at the same as when a status interrupt request signal (INTLSn) is generated and a data consistency error flag is set (UFnDCE = 1). Remarks 1. See (2) of 13.11 Cautions on Use for details of starting LIN-UART. 2. n = 0, 1 R01UH0317EJ0004 Rev. 0.04 720 Feb. 22, 2013 No No
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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34.2 64-pin products 1276 R5F10CLDx
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