RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) (19) Port mode registers 1, 7, 13 (PM1, PM7, PM13) The PM1, PM7 and PM13 registers are used to set ports 1, 7, and 13 to input or output in 1-bit units. The PM1, PM7 and PM13 registers can be set by using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH (PM13 is set to FEH). Caution The shaded pins are provided at two ports. Select either port by using the corresponding register. Remarks 1. The pins mounted depend on the product. See 1.4 Ordering Information and 2.1 Pin Function List. 2. See CHAPTER 4 PORT FUNCTIONS for port settings. Figure 13-20. Format of Port Mode Registers 1, 7, 13 (PM1, PM7, PM13) Address: FFF21H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 Address: FFF27H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM7 PM77 PM76 PM75 PM74 PM73 PM72 PM71 PM70 Address: FFF2DH After reset: FEH R/W Symbol 7 6 5 4 3 2 1 0 PM13 1 PM136 PM135 PM134 PM133 PM132 PM131 0 PMmn PMmn pin I/O mode selection (m = 1, 7; n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) R01UH0317EJ0004 Rev. 0.04 715 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) 13.4 Interrupt Request Signals The following three interrupt request signals are generated from LIN-UARTn. Status interrupt request signal (INTLSn) Reception complete interrupt request signal (INTLRn) Transmission interrupt request signal (INTLTn) Table 13-2 shows the default priority order of these three interrupt request signals. Table 13-2. Interrupts and Their Default Priorities Interrupt Default Priority Status Low Reception complete Transmission start/complete High (1) Status interrupt request signal (INTLSn) A status interrupt request signal is generated when an error condition is detected during a reception. A UFnSTR register flag (UFnPE, UFnFE, UFnOVE, UFnDCE, UFnBSF, UFnIPE, UFnCSE, UFnRPE, UFnIDM, UFnEBD) corresponding to the detected status is set. See 13.5.10 Status interrupt generation sources for details. (2) Reception complete interrupt request signal (INTLRn) A reception complete interrupt request signal is generated when data is shifted into the receive shift register and transferred to the UFnRX register in the reception enabled status. When a reception error occurs, a reception complete interrupt request signal is not generated, but a status interrupt request signal is generated. No reception complete interrupt request signal is generated in the reception disabled status. If expansion bit operation is enabled (UFnCL = UFnEBE = 1) and expansion bit data comparison is disabled (UFnEBC = 0), a reception complete interrupt request signal is generated when the level of the inverted value set by using the expansion bit detection level select bit (UFnEBL) is detected as an expansion bit. When there is no error when in automatic baud rate mode (UFnMD1, UFnMD0 = 11B) and PID reception has been completed (stop bit position), a reception complete interrupt request signal is generated. When response reception or response transmission has ended without an error when in automatic baud rate mode (UFnMD1, UFnMD0 = 11B), a transmission complete interrupt request signal is generated. Remark n = 0, 1 R01UH0317EJ0004 Rev. 0.04 716 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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