RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 14 CAN CONTROLLER
(b) Write
Figure 14-45. Format of CAN Module Time Stamp Register (C0TS, C1TS) (2/2)
TSSEL Time Stamp Capture Event Selection Bit
0 The time stamp capture event is SOF.
1 The time stamp capture event is the last bit of EOF.
TSEN TSOUT Signal Operation Setting Bit
0 Disable TSOUT signal toggle operation.
1 Enable TSOUT signal toggle operation.
Remark The signal TSOUT is output from the CAN macro to a timer resource, depending on
implementation. Refer to CHAPTER 6 TIMER ARRAY UNIT.
Set TSLOCK Clear
TSLOCK
0 1 TSLOCK bit is cleared to 0.
1 0 TSLOCK bit is set to 1.
Other than above TSLOCK bit is not changed.
Setting of TSLOCK Bit
Set TSSEL Clear TSSEL Setting of TSSEL Bit
0 1 TSSEL bit is cleared to 0.
1 0 TSSEL bit is set to 1.
Other than above TSSEL bit is not changed.
Set TSEN Clear TSEN Setting of TSEN Bit
0 1 TSEN bit is cleared to 0.
1 0 TSEN bit is set to 1.
Other than above TSEN bit is not changed.
R01UH0317EJ0004 Rev. 0.04 871
Feb. 22, 2013