RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 6 TIMER ARRAY UNIT
(c) Start timing in capture mode
Writing 1 to TSmn sets TEmn = 1.
The write data to TSmn is held until count clock generation.
TCRmn holds the initial value until count clock generation.
On generation of count clock, 0000H is loaded to TCRmn and count starts.
Figure 6-17. Start Timing (In Capture Mode)
fCLK
TSmn (write)
TEmn
Count clock
TSmn (write) hold signal
Start trigger detection signal
TCRmn
INTTMmn
Initial value
0000H
When MDmn0 = 1 is set
Caution In the first cycle operation of count clock after writing TSmn, an error at a maximum of one clock
is generated since count start delays until count clock has been generated. When the
information on count start timing is necessary, an interrupt can be generated at count start by
setting MDmn0 = 1.
Remark m: Unit number (m = 0 to 2)
n: Channel number (n = 0 to 7)
R01UH0317EJ0004 Rev. 0.04 341
Feb. 22, 2013