RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) Target Baud Rate (bps) Table 13-7. Baud Rate Generator Setting Data (Normal Operation, fCLK = 16 MHz, UFnPRS2 to UFnPRS0 = 0 to 3) (1/2) UFnPRS2 to UFnPRS0 0 1 2 3 UFnBRS11 to ERR UFnBRS11 to ERR UFnBRS11 ERR UFnBRS11 to UFnBRS00 (%) UFnBRS00 (%) to UFnBRS00 (%) UFnBRS00 300 3333 0.01 600 3333 0.01 1667 -0.02 1200 3333 0.01 1667 -0.02 833 0.04 2400 3333 0.01 1667 -0.02 833 0.04 417 -0.08 4800 1667 -0.02 833 0.04 417 -0.08 208 0.16 9600 833 0.04 417 -0.08 208 0.16 104 0.16 19200 417 -0.08 208 0.16 104 0.16 52 0.16 31250 256 0.00 128 0.00 64 0.00 32 0.00 38400 208 0.16 104 0.16 52 0.16 26 0.16 76800 104 0.16 52 0.16 26 0.16 13 0.16 128000 63 -0.79 31 0.81 16 -2.34 8 -2.34 153600 52 0.16 26 0.16 13 0.16 7 -6.99 312500 26 -1.54 13 -1.54 6 6.67 1000000 8 0.00 4 0.00 Target Baud Rate (bps) Table 13-7. Baud Rate Generator Setting Data (Normal Operation, fCLK = 16 MHz, UFnPRS2 to UFnPRS0 = 4 to 7) (2/2) UFnPRS2 to UFnPRS0 4 5 6 7 UFnBRS11 to ERR UFnBRS11 to ERR UFnBRS11 to ERR UFnBRS11 to UFnBRS00 (%) UFnBRS00 (%) UFnBRS00 (%) UFnBRS00 300 1667 -0.02 833 0.04 417 -0.08 208 0.16 600 833 0.04 417 -0.08 208 0.16 104 0.16 1200 417 -0.08 208 0.16 104 0.16 52 0.16 2400 208 0.16 104 0.16 52 0.16 26 0.16 4800 104 0.16 52 0.16 26 0.16 13 0.16 9600 52 0.16 26 0.16 13 0.16 7 -6.99 19200 26 0.16 13 0.16 7 -6.99 31250 16 0.00 8 0.00 4 0.00 38400 13 0.16 7 -6.99 76800 7 -6.99 128000 4 -2.34 153600 312500 1000000 R01UH0317EJ0004 Rev. 0.04 777 Feb. 22, 2013 ERR (%) ERR (%)
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) Target Baud Rate (bps) Table 13-8. Baud Rate Generator Setting Data (Normal Operation, fCLK = 8 MHz, UFnPRS2 to UFnPRS0 = 0 to 3) (1/2) UFnPRS2 to UFnPRS0 0 1 2 3 UFnBRS11 to ERR UFnBRS11 to ERR UFnBRS11 to ERR UFnBRS11 to UFnBRS00 (%) UFnBRS00 (%) UFnBRS00 (%) UFnBRS00 300 3333 0.01 1667 -0.02 600 3333 0.01 1667 -0.02 833 0.04 1200 3333 0.01 1667 -0.02 833 0.04 417 -0.08 2400 1667 -0.02 833 0.04 417 -0.08 208 0.16 4800 833 0.04 417 -0.08 208 0.16 104 0.16 9600 417 -0.08 208 0.16 104 0.16 52 0.16 19200 208 0.16 104 0.16 52 0.16 26 0.16 31250 128 0.00 64 0.00 32 0.00 16 0.00 38400 104 0.16 52 0.16 26 0.16 13 0.16 76800 52 0.16 26 0.16 13 0.16 7 -6.99 128000 31 0.81 16 -2.34 8 -2.34 4 -2.34 153600 26 0.16 13 0.16 7 -6.99 312500 13 -1.54 6 6.67 1000000 4 0.00 Target Baud Rate (bps) Table 13-8. Baud Rate Generator Setting Data (Normal Operation, fCLK = 8 MHz, UFnPRS2 to UFnPRS0 = 4 to 7) (2/2) UFnPRS2 to UFnPRS0 4 5 6 7 UFnBRS11 to ERR UFnBRS11 to ERR UFnBRS11 to ERR UFnBRS11 to UFnBRS00 (%) UFnBRS00 (%) UFnBRS00 (%) UFnBRS00 300 833 0.04 417 -0.08 208 0.16 104 0.16 600 417 -0.08 208 0.16 104 0.16 52 0.16 1200 208 0.16 104 0.16 52 0.16 26 0.16 2400 104 0.16 52 0.16 26 0.16 13 0.16 4800 52 0.16 26 0.16 13 0.16 7 -6.99 9600 26 0.16 13 0.16 7 -6.99 19200 13 0.16 7 -6.99 31250 8 0.00 4 0.00 38400 7 -6.99 76800 128000 153600 312500 1000000 R01UH0317EJ0004 Rev. 0.04 778 Feb. 22, 2013 ERR (%) ERR (%)
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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