RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L, IF3H) (R5F10DPJxFB) (2/2) Address: FFFD1H After reset: 00H R/W Symbol IF2H FLIF C1RECIF MDIF TMIF13 TMIF12 TMIF11 TMIF10 C0TRXIF Address: FFFD2H After reset: 00H R/W Symbol IF3L TMIF22 TMIF21 TMIF20 TMIF17 TMIF16 TMIF15 TMIF14 C1TRXIF Address: FFFD3H After reset: 00H R/W Symbol 7 6 5 IF3H 0 0 0 DMAIF3 DMAIF2 TMIF26 TMIF24 TMIF23 XXIFX Interrupt request flag 0 No interrupt request signal is generated 1 Interrupt request is generated, interrupt request status Cautions 1. The above is the bit layout for the R5F10DPJxFB. The available bits differ depending on the product. For details about the bits available for each product, see Table 20-1 and 20-2. Be sure to clear bits that are not available to 0. 2. When manipulating a flag of the interrupt request flag register, use a 1-bit memory manipulation instruction (CLR1). When describing in C language, use a bit manipulation instruction such as “IF0L.0 = 0;” or “_asm(“clr1 IF0L, 0”);” because the compiled assembler must be a 1-bit memory manipulation instruction (CLR1). If a program is described in C language using an 8-bit memory manipulation instruction such as “IF0L &= 0xfe;” and compiled, it becomes the assembler of three instructions. mov a, IF0L and a, #0FEH mov IF0L, a In this case, even if the request flag of the another bit of the same interrupt request flag register (IF0L) is set to 1 at the timing between “mov a, IF0L” and “mov IF0L, a”, the flag is cleared to 0 at “mov IF0L, a”. Therefore, care must be exercised when using an 8-bit memory manipulation instruction in C language. (2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L, MK3H) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. The MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L, and MK3H registers can be set by a 1-bit or 8-bit memory manipulation instruction. When the MK0L and MK0H registers, the MK1L and MK1H registers, the MK2L and MK2H registers, and the MK3L and MK3H registers are combined to form 16-bit registers MK0, MK1, MK2, and MK3, they can be set by a 16-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks increases by 2 clocks. R01UH0317EJ0004 Rev. 0.04 1057 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 20 INTERRUPT FUNCTIONS Figure 20-3. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L, MK3H) (R5F10DPJxFB) Address: FFFE4H After reset: FFH R/W Symbol MK0L PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 LVIMK WDTIMK Address: FFFE5H After reset: FFH R/W Symbol MK0H LTMK0 ITMK RTCMK DMAMK1 DMAMK0 CSIMK01 CSIMK00 CLMMK Address: FFFE6H After reset: FFH R/W Symbol MK1L TMMK03 TMMK02 TMMK01 TMMK00 SGMK PMKLR0 LSMK0 LRMK0 Address: FFFE7H After reset: FFH R/W Symbol MK1H TMMK04 IICMK11 CSIMK10 PMKLR1 LSMK1 LRMK1 LTMK1 ADMK Address: FFFD4H After reset: FFH R/W Symbol MK2L C0RECMK C0WUPMK C0ERRMK C1WUPMK C1ERRMK TMMK07 TMMK06 TMMK05 Address: FFFD5H After reset: FFH R/W Symbol MK2H FLMK C1RECMK MDMK TMMK13 TMMK12 TMMK11 TMMK10 C0TRXMK Address: FFFD6H After reset: FFH R/W Symbol MK3L TMMK22 TMMK21 TMMK20 TMMK17 TMMK16 TMMK15 TMMK14 C1TRXMK Address: FFFD7H After reset: FFH R/W Symbol 7 6 5 MK3H 1 1 1 DMAMK3 DMAMK2 TMMK26 TMMK24 TMMK23 XXMKX Interrupt servicing control 0 Interrupt servicing enabled 1 Interrupt servicing disabled Caution The above is the bit layout for the R5F10DPJxFB. The available bits differ depending on the product. For details about the bits available for each product, see Table 20-1 and 20-2. Be sure to set bits that are not available to 1. R01UH0317EJ0004 Rev. 0.04 1058 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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