RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
When transferring the number of bytes (1 to 9) set to the buffer length bit (UFnBUL3 to UFnBUL0) has ended, a
transmission interrupt request signal (INTLTn) is output. When the buffer length bit is set to “0” or “10 to 15”, transfer of
nine bytes is performed.
Writing data to the transmit data register (UFnTX) during transmission in buffer mode is prohibited.
To stop transfer midway, write “0” to the transmission enable bit (UFnTXE). Data transmission processing is stopped
and the UFnTRQ bit and UFnTSF flag are cleared.
UFnTRQ bit
UFnBUL3 to UFnBUL0 bits
(write)
UFnBUL3 to UFnBUL0 bits
(read)
UFnTSF flag
LTxDn pin
INTLTn
(UFnITS = 0)
UFnBUC flag
UFnTRQ bit
UFnBUL3 to UFnBUL0 bits
(write)
UFnBUL3 to UFnBUL0 bits
(read)
UFnTSF flag
LTxDn pin
INTLTn
(UFnITS = 1)
UFnBUC flag
Figure 13-50. UART Buffer Mode Transmission Example (UFnITS = 0)
Set
Sets UFnTRQ bit to 1
Prepare next TX
R01UH0317EJ0004 Rev. 0.04 751
Feb. 22, 2013
Set
0 m
0 1 2 3 8 9 0 1 2 3 m
1st data 2nd data 7th data 8th data 9th data
1st data 2nd data (m−1)th data (m)th data
Clear
Figure 13-51. UART Buffer Mode Transmission Example (UFnITS = 1)
Set
Remark n = 0, 1, m = 1 to 9
Sets UFnTRQ bit to 1
Set
Clear
Prepare next TX
Prepare next TX
Sets UFnCLBUC bit to 1
0 m
0 1 2 7 8 9 0 1 2 m−1 m
1st data 2nd data 7th data 8th data 9th data
1st data 2nd data (m−1)th data (m)th data
Clear
Clear
Sets UFnCLBUC bit to 1
Prepare next TX