RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT (2) Processing flow (a) When starting data reception SSmn STmn SEmn SOEmn SDRmn SCLr output SDAr output SDAr input Shift register mn INTIICr TSFmn “H” TXEmn, TXEmn = 1 / RXEmn = 0 RXEmn (b) When receiving last data STmn SEmn SOEmn TXEmn, RXEmn SDRmn SCLr output SDAr output SDAr input Shift register mn INTIICr TSFmn Output is enabled by serial communication operation D2 D1 D0 ACK Figure 12-80. Timing Chart of Data Reception TXEmn = 0 / RXEmn = 1 Dummy data (FFH) Receive data D7 D6 D5 D4 D3 D2 D1 D0 R01UH0317EJ0004 Rev. 0.04 663 Feb. 22, 2013 Shift operation Output is stopped by serial communication operation TXEmn = 0 / RXEmn = 1 Dummy data (FFH) Receive data Dummy data (FFH) Receive data Shift operation D7 D6 D5 D4 D3 D2 D1 D0 Shift operation Reception of last byte Remark m: Unit number (m = 1), n: Channel number (n = 1), r: IIC number (r = 11) NACK ACK SOmn bit manipulation IIC operation stop Stop condition SOmn bit manipulation CKOmn bit manipulation
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT No Figure 12-81. Flowchart of Data Reception Address field transmission completed Writing 1 to STmn bit Writing 0 to TXEmn bit, and 1 to RXEmn bit Writing 1 to SSmn bit Starting data reception Last byte received? No Writing dummy data (FFH) to SDRmn Transfer end interrupt generated? Yes Reading SDRmn Data transfer completed? Yes Data reception completed Stop condition generation Caution ACK is not output when the last data is received (NACK). Communication is then completed by setting “1” to the STmn bit to stop operation and generating a stop condition. R01UH0317EJ0004 Rev. 0.04 664 Feb. 22, 2013 Yes Writing 0 to SOEmn bit (Stopping output by serial communication operation) No
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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14.9.1 Message reception ..........
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19.2 Configuration of DMA Controlle
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28.1.1 Programming Environment.....
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34.2 64-pin products 1276 R5F10CLDx
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34.4 100-pin products 1278 CHAPTER
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RL78/D1A User’s Manual: Hardware
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