RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) A transmission operation is started by writing transmit data to the transmit data register (UFnTX). The data stored into the UFnTX register is transferred to the transmit shift register and a start bit, an expansion bit, a parity bit, and stop bits are added to the data, and the data are sequentially output from the LTxDn pin. If a transmission interrupt is set upon starting a transmission (UFnITS = 0), a transmission interrupt request signal (INTLTn) is generated when transferring the data stored into the UFnTX register to the transmit shift register has been completed. If a transmission interrupt is set upon completion of a transmission (UFnITS = 1), a transmission interrupt request signal (INTLTn) is generated when transmitting a stop bit has been completed. fCLK LTxDn pin Prescaler clock Transmission baud rate clock INTLTn (UFnITS = 0) INTLTn (UFnITS = 1) UFnTSF flag Figure 13-23. Data Transmission Timing Chart START DT0 STOP1 Transmission processing start Transmission baud rate period Set by writing UFnTX register Transmission baud rate period Transmission processing end Transmission baud rate period Cleared when next transmit data does not exist Caution If the stop bit length is set to 2 bits (UFnSL = 1), the transmit completion interrupt (INTLTn) will be output after the second stop bit has been transmitted, at which point the transmission status flag (UFnTSF) will be cleared. Remark n = 0, 1 R01UH0317EJ0004 Rev. 0.04 721 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) When generation of a transmission interrupt is set upon starting a transmission (UFnITS = 0), successive transmission can be performed by writing the next data to UFnTX during the transmission after INTLTn has been generated. Figure 13-24. Diagram of Timing When Starting Successive Transmission (UFnITS = 0) LTxDn pin UFnTX register Transmit shift register INTLTn UFnTSF flag LTxDn pin Start Data (1) Data (1) Data (1) Parity Stop Start Data (2) Parity Stop Start Data (2) Data (2) Data (3) Figure 13-25. Diagram of Timing When Ending Successive Transmission (UFnITS = 0) UFnTX register Transmit shift register INTLTn UFnTSF flag Remark n = 0, 1 Parity Stop Start Data (n – 1) Parity Stop Start Data (n) Parity Stop Data (n – 1) Data (n) Data (n – 1) Data (n) FFH UFnTXE bit R01UH0317EJ0004 Rev. 0.04 722 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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34.2 64-pin products 1276 R5F10CLDx
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