RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) (2) Early end of reception processing When transmission is performed while reception is enabled (UFnTXE = UFnRXE = 1), a stop bit position detected in the reception processing, even though during transmission is judged as being abnormal and the UFnDCE bit is set (1) at the same time a status interrupt (INTLSn) is generated. Figure 13-39. Timing Example of Consistency Error Occurrence due to Early End of Reception Processing LTxDn output (D5H) LRxDn input (AAH) Data sampling UFnTSF flag Error judgment (internal signal) UFnDCE flag INTLSn Remark n = 0, 1 Start bit Start bit D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 Next transmission is not performed. D5 D6 D7 R01UH0317EJ0004 Rev. 0.04 739 Feb. 22, 2013 Stop bit Reception end Stop bit
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF) 13.5.9 BF reception mode select function A mode for BF (break field) reception, which can be selected by using the LIN-UART operation mode selection bits (UFnMD1, UFnMD0), is provided. (1) Normal UART mode (UFnMD1 and UFnMD0 = 00B) In normal UART mode (UFnMD1 and UFnMD0 = 00B), a new BF is only recognized when the system is waiting for a BF to be successfully received (UFnBRF = 1). If the system is not waiting for a BF to be successfully received (UFnBRF = 0), framing or overrun errors are detected at the data’s stop bit position (bit 10) (see Figure 13-42). If an overrun error has not occurred, the received data is stored in the UFnRX register. If the system is waiting for a BF to be successfully received (UFnBRF = 1), framing or overrun errors are not detected and the received data is not stored in the UFnRX register. If UFnBRF = 0 and reception is stopped when data or the BF stop bit is transmitted, the data consistency error interrupt is issued and the flag is changed when transmission of the bit following the stop bit starts (see 13.5.8 (2)). If reception is in progress when the stop bit is transmitted, the data consistency error interrupt is issued and the flag is changed when transmission of the stop bit starts (see 13.5.8 (1)). On the other hand, if UFnBRF = 1 and reception is stopped when the stop bit is transmitted, the data consistency error interrupt is issued and the flag is changed when transmission of the bit following the stop bit starts (see Figure 13-43) and if reception is in progress when the stop bit is transmitted, the data consistency error interrupt is issued and the flag is changed when the rising edge of the input data following the stop bit is detected (see Figure 13-44). LRxDn input Data sampling UFnFE flag, UFnOVE flag INTLSn Caution The successful BF reception flag (UFnBSF) is not set in normal UART mode. Figure 13-40. Timing of Judging Framing or Overrun Error in Normal UART Mode Start bit D0 D1 D4 D5 D6 D7 R01UH0317EJ0004 Rev. 0.04 740 Feb. 22, 2013 Stop bit
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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19.2 Configuration of DMA Controlle
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RL78/D1A User’s Manual: Hardware
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