RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 21 STANDBY FUNCTION 21.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the setting was the high-speed on-chip oscillator clock, X1 clock, PLL clock or external main system clock. Cautions 1. Because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction and the system returns to the operating mode as soon as the wait time set using the oscillation stabilization time select register (OSTS) has elapsed. 2. When using the A/D converter in the SNOOZE mode, set up A/D converter mode register 2 (ADM2) before switching to the STOP mode. For details, see 11.3 Registers Used in A/D Converter. The operating statuses in the STOP mode are shown below. R01UH0317EJ0004 Rev. 0.04 1083 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 21 STANDBY FUNCTION Item STOP Mode Setting Table 21-2. Operating Statuses in STOP Mode (1/2) When STOP Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on High-speed on-chip oscillator Clock (fIH) System clock Clock supply to the CPU is stopped Main system clock fIH fX fEX Stopped Subsystem clock fXT Status before STOP mode was set is retained When CPU Is Operating on X1 Clock (fX) When CPU Is Operating on External Main System Clock (fEX) fIL Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of operation speed mode control register (OSMC) WUTMMCK0 = 1: Oscillates WUTMMCK0 = 0 and WDTON = 0: Stops WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 1: Oscillates WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 0: Stops PLL Operation disabled CPU Code flash memory Operation stopped Data flash memory Operation stopped (The STOP instruction is not executed during data flash programming) RAM Operation stopped CREG Low power mode Port (latch) Status before STOP mode was set is retained Timer array unit Operation disabled Real-time clock (RTC) Operable by fXT or fIL Interval timer Watchdog timer See CHAPTER 10 WATCHDOG TIMER CLM Operation stopped PCL Operable only when fXT clock is selected A/D converter Operation stopped Serial array unit (SAU) Operation disabled SAU (CSI, IIC) Operation stopped Serial interface LIN-UART (UARTF) Operation disabled (STOP release by INTPLRx is possible) CAN controller Operation disabled (STOP release by INTCxWUP during CAN sleep mode is possible) LCD controller/driver Operable by fXT or fIL Sound generator Stepper motor controller/driver (with ZPD) Multiplier and divider/multiplyaccumulator DMA controller Power-on-reset function Voltage detection function Operation stopped Operation disabled Operable External interrupt Acceptable Internal interrupt Interrupts from operable peripherals are acceptable R01UH0317EJ0004 Rev. 0.04 1084 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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34.2 64-pin products 1276 R5F10CLDx
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RL78/D1A User’s Manual: Hardware
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