RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 21 STANDBY FUNCTION Table 21-3. Operating Statuses in SNOOZE Mode (2/2) SNOOZE Mode Setting When Inputting A/D Converter Timer Trigger Signal While in SNOOZE Mode Item When CPU Is Operating on High-speed on-chip oscillator Clock (fIH) CRC operation function High-speed CRC General-purpose CRC Illegal access detection function RAM parity check function RAM guard function SFR guard function Operation disabled BCD Remark Operation stopped: Operation is automatically stopped before switching to the SNOOZE mode. Operation disabled: Operation is stopped before switching to the SNOOZE mode. fIH: High-speed on-chip oscillator clock fIL: Low-speed on-chip oscillator clock fX: X1 clock fXT: XT1 clock fEX: External main system clock R01UH0317EJ0004 Rev. 0.04 1091 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 22 RESET FUNCTION CHAPTER 22 RESET FUNCTION The following eight operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by comparison of supply voltage and detection voltage of power-on-reset (POR) circuit (4) Internal reset by comparison of supply voltage of the voltage detector (LVD) and detection voltage (5) Internal reset by execution of illegal instruction Note (6) Internal reset by RAM parity error (7) Internal reset by detection of main clock oscillation stop via clock monitoring (8) Internal reset by illegal-memory access External and internal resets start program execution from the address at 0000H and 0001H when the reset signal is generated. A reset is effected when a low level is input to the RESET pin, the watchdog timer overflows, or by POR and LVD circuit voltage detection, execution of illegal instruction Note , RAM parity error, detection of main clock oscillation stop via clock monitoring, or illegal-memory access, and each item of hardware is set to the status shown in Tables 22-1. When a low level is input to the RESET pin, the device is reset. It is released from the reset status when a high level is input to the RESET pin and program execution is started with the high-speed on-chip oscillator clock after reset processing. A reset by the watchdog timer is automatically released, and program execution starts using the high-speed on-chip oscillator clock (see Figures 22-2 to 22-4) after reset processing. Reset by POR and LVD circuit supply voltage detection is automatically released when VDD VPOR or VDD VLVD after the reset, and program execution starts using the high-speed on-chip oscillator clock (see CHAPTER 23 POWER-ON-RESET CIRCUIT and CHAPTER 24 VOLTAGE DETECTOR) after reset processing. Note The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. Cautions 1. For an external reset, input a low level for 10 s or more to the RESET pin. (To perform an external reset upon power application, a low level of at least 10 s must be continued during the period in which the supply voltage is within the operating range (VDD 2.7 V).) 2. During reset input, the X1 clock, XT1 clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock stop oscillating. External main system clock input becomes invalid. 3. When reset is effected, port pin P130 is set to low-level output and other port pins become highimpedance, because each SFR and 2nd SFR are initialized. Remark VPOR: POR power supply rise detection voltage R01UH0317EJ0004 Rev. 0.04 1092 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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19.2 Configuration of DMA Controlle
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RL78/D1A User’s Manual: Hardware
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