RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 11 A/D CONVERTER
11.6.4 Software trigger mode (scan mode, one-shot conversion mode)
In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
A/D conversion standby status.
After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to
perform A/D conversion on the four analog input channels specified by scan 0 to scan 3, which are specified by
the analog input channel specification register (ADS). A/D conversion is performed on the analog input channels
in order, starting with that specified by scan 0.
A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in
the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end
interrupt request signal (INTAD) is generated.
After A/D conversion of the four channels ends, the ADCS bit is automatically cleared to 0, and the system enters
the A/D conversion standby status.
When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts at the first channel. The partially converted data is discarded.
When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register.
The partially converted data is discarded.
When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the
system enters the A/D conversion standby status.
When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status.
When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start. In addition, A/D
conversion does not start even if a hardware trigger is input while in the A/D conversion standby status.
Figure 11-22. Example of Software Trigger Mode (Scan Mode, One-Shot Conversion Mode) Operation Timing
ADCE
The trigger
is not
acknowledged.
ADCS
ADS
A/D
conversion
status
ADCR,
ADCRH
INTAD
Stop
status
ADCE is set to 1.
ADCS is set to 1 while
in the conversion
standby status.
ANI0 to ANI3
Conversion
standby
Data 0
(ANI0)
Data 1
(ANI1)
Data 0
(ANI0)
Data 2
(ANI2)
Data 1
(ANI1)
Data 3
(ANI3)
Data 2
(ANI2)
ADCS is
automatically
cleared to
0 after
conversion
ends.
ADCS is overwritten
with 1 during A/D
conversion operation.
A/D conversion
ends.
Conversion
standby
Data 3
(ANI3)
Data 0 Data 1
(ANI0) (ANI1)
Conversion is
interrupted and restarts.
Data 0
(ANI0)
Data 0 (ANI0)
Data 1
(ANI1)
Conversion
standby
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Data 2
(ANI2)
Data 1
(ANI1)
Data 3
(ANI3)
Data 2
(ANI2)
The interrupt is generated four times. The interrupt is generated four times.
Data 3
(ANI3)
Data 0
(ANI0)
Data 1
(ANI1)
Data 4
(ANI4)
Data 0
(ANI0)
ADCS is cleared
to 0 during A/D
conversion operation.
ADS is rewritten during
A/D conversion operation.
ANI4 to ANI7
Conversion is
interrupted and restarts.
Data 5
(ANI5)
Data 4
(ANI4)
ADCE is cleared to 0.
Data 6
(ANI6)
Data 5
(ANI5)
Data 7
(ANI7)
Conversion is
interrupted.
Conversion
standby
Data 6
(ANI6)
The trigger
is not
acknowledged.
Stop
status