RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 14 CAN CONTROLLER
(24) CAN message control register m (C0MCTRLm, C1MCTRLm)
The C0MCTRLm, C1MCTRLm register is used to control the operation of the message buffer.
(a) Read
(b) Write
(a) Read
Figure 14-50. Format of CAN Message Control Register m (C0MCTRLm, C1MCTRLm) (1/3)
Address: See Table 14-16. After reset: 00x00000 R/W
000xx000B
C0MCTRLm,
C1MCTRLm
C0MCTRLm,
C1MCTRLm
15 14 13 12 11 10 9 8
0 0 MUC 0 0 0 0 0
7 6 5 4 3 2 1 0
0 0 0 MOW IE DN TRQ RDY
15 14 13 12 11 10 9 8
0 0 0 0 Set
IE
0 Set
TRQ
7 6 5 4 3 2 1 0
0 0 0 Clear
MOW
R01UH0317EJ0004 Rev. 0.04 877
Feb. 22, 2013
Clear
IE
Clear
DN
MUC Note Message Buffer Data Updating Bit
Clear
TRQ
0 The CAN module is not updating the message buffer (reception and storage).
1 The CAN module is updating the message buffer (reception and storage).
Note The MUC bit is undefined until the first reception and storage is performed.
MOW Message Buffer Overwrite Status Bit
0 The message buffer is not overwritten by a newly received data frame.
1 The message buffer is overwritten by a newly received data frame.
Set
RDY
Clear
RDY
Remark MOW bit is not set to 1 even if a remote frame is received and stored in the transmit
message buffer with DN = 1.
IE Message Buffer Interrupt Request Enable Bit
0 Receive message buffer: Valid message reception completion interrupt disabled.
Transmit message buffer: Normal message transmission completion interrupt disabled.
1 Receive message buffer: Valid message reception completion interrupt enabled.
Transmit message buffer: Normal message transmission completion interrupt enabled.
Remark m = 0 to 15