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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)<br />

Figure 13-5. Format of LIN-UARTn Option Register 1 (UFnOPT1) (2/3)<br />

UFnEBC Expansion bit data comparison enable bit<br />

0 No comparison<br />

(INTLRn or INTLSn is always generated upon completion of data reception.)<br />

1 Compares UFnRX register and UFnID register when the level selected for the UFnEBL<br />

bit has been detected as the expansion bit.<br />

(INTLSn is generated only when the UFnRX register and UFnID register have<br />

matched.)<br />

The UFnEBC bit is used to enable comparison between the received data and the UFnID register<br />

when the expansion bit has been enabled (UFnCL = UFnEBE = 1).<br />

Remark The UFnEBC bit becomes valid only if UFnCL = UFnEBE = 1. See 13.8.2 Expansion bit<br />

mode reception (no data comparison) and 13.8.3 Expansion bit mode reception<br />

(with data comparison) for details.<br />

UFnIPCS ID parity check select bit<br />

0 No automatic ID parity check<br />

(Calculating the parity of the PID by using software and checking are required.)<br />

1 Automatic ID parity check<br />

The UFnIPCS bit is used to select how to handle automatic checking of the parity bit of the<br />

received PID, when in automatic baud rate mode (UFnMD1, UFnMD0 = 11B).<br />

If UFnIPCS is “1”, the parity bit is checked when the PID received in LIN communication is stored<br />

into the UFnID register. When an incorrect result has been detected, an ID parity error flag<br />

(UFnIPE) will be set and a status interrupt request signal (INTLSn) will be generated.<br />

Remark The UFnIPCS bit becomes valid only in the automatic baud rate mode (UFnMD1,<br />

UFnMD0 = 11B). See 13.7.3 ID parity check function for details.<br />

UFnACE Automatic checksum enable bit<br />

0 Disables automatic checksum calculation.<br />

Response transmission: Checksum must be calculated by using software and set to a<br />

buffer.<br />

Response reception: Checksum must be calculated from the data stored into the<br />

buffer by using software, and compared and checked with the<br />

checksum obtained via communication.<br />

1 Enables automatic checksum calculation.<br />

Response transmission: Checksum is automatically calculated from the data set to a<br />

buffer and is automatically appended at the end of response<br />

transmission.<br />

Response reception: Checksum is automatically calculated from the data stored<br />

into the buffer and is automatically compared and checked<br />

with the checksum obtained via communication.<br />

The UFnACE bit is used to select how to handle automatic checksum calculation during response<br />

transmission and response reception, when in automatic baud rate mode (UFnMD1, UFnMD0 =<br />

11B).<br />

When response reception is performed while UFnACE is “1”, the checksum received in LIN<br />

communication will be checked when it is stored into a receive buffer. When an incorrect result<br />

has been detected, a checksum error flag (UFnCSE) will be set and a status interrupt request<br />

signal (INTLSn) will be generated.<br />

Remark The UFnACE bit becomes valid only in the automatic baud rate mode (UFnMD1, UFnMD0<br />

= 11B). See 13.7.4 Automatic checksum function for details.<br />

R01UH0317EJ0004 Rev. 0.04 692<br />

Feb. 22, 2013

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