RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
Figure 13-7. Format of LIN-UARTn Status Register (UFnSTR) (3/6)
UFnBUC Buffer transmission/reception completion flag
0 Buffer transmission/reception is not completed.
1 Buffer transmission/reception is completed
The set number of data is transmitted or received.
(only when transmitted when in normal UART mode)
The UFnBUC bit is a flag indicating the data transmission and reception status of a buffer. It
becomes “1” when the set number of data items have been transmitted or received
without an error occurring. See 13.6.1 UART buffer mode transmission and 13.7 LIN
Communication Automatic Baud Rate Mode for details.
The UFnBUC bit will not be cleared until “1” is written to the UFnCLBUC bit of the UFnSTC
register, because the UFnBUC bit is a cumulative flag. It will be set only when in normal UART
mode (UFnMD1, UFnMD0 = 00B) or automatic baud rate mode (UFnMD1, UFnMD0 = 11B).
UFnIDM ID match flag
0 The ID does not match.
1 The IDdoes match
When 8 bits of receive data, excluding expansion bit, have matched with UFnID
register value set in advance
The UFnIDM bit is a flag indicating the result of comparing the 8 bits of receive data, excluding
the expansion bit, and the UFnID register value set in advance when expansion bit data
comparison has been enabled (UFnEBC = 1) by enabling the expansion bit (UFnCL = UFnEBE =
1). The comparison will be performed with the data for which the level set by using the expansion
bit detection level select bit (UFnEBL) has been detected. The UFnIDM bit becomes “1” when the
comparison result has matched. See 13.8.3 Expansion bit mode reception (with data
comparison) for details.
The UFnIDM bit will not be cleared until “1” is written to the UFnCLIDM bit of the UFnSTC
register, because the UFnIDM bit is a cumulative flag. It will not be set when the expansion bit
has not been enabled and expansion bit data comparison has not been enabled (UFnCL =
UFnEBE = UFnEBC = 1).
UFnEBD Expansion bit detection flag
0 An extension bit is not detected
1 An extension bit is detected
When level set by using expansion bit detection level select bit (UFnEBL) has been
detected for expansion bit
The UFnEBD bit is a flag indicating detection of the level set by using the expansion bit detection
level select bit (UFnEBL) when the expansion bit has been enabled (UFnCL = UFnEBE = 1). It
becomes “1” when the setting level has been detected. See 13.8.2 Expansion bit mode
reception (no data comparison) and 13.8.3 Expansion bit mode reception (with data
comparison) for details.
The UFnEBD bit will not be cleared until “1” is written to the UFnCLEBD bit of the UFnSTC
register, because the UFnEBD bit is a cumulative flag. It will not be set when the expansion bit
has been disabled (UFnEBE = 0).
R01UH0317EJ0004 Rev. 0.04 697
Feb. 22, 2013