RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 3 CPU ARCHITECTURE SP←SP−2 ↑ SP−2 ↑ SP−1 ↑ SP → SP←SP−4 ↑ SP−4 ↑ SP−3 ↑ SP−2 ↑ SP−1 ↑ SP → Figure 3-18. Data to Be Saved to Stack Memory PUSH rp instruction Register pair lower Register pair higher CALL, CALLT instructions (4-byte stack) PC7 to PC0 PC15 to PC8 PC19 to PC16 00H SP←SP−2 ↑ SP−2 ↑ SP−1 ↑ SP → SP←SP−4 ↑ SP−4 ↑ SP−3 ↑ SP−2 ↑ SP−1 ↑ SP → PUSH PSW instruction Interrupt, BRK instruction (4-byte stack) PC7 to PC0 PC15 to PC8 PC19 to PC16 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FFEE0H to FFEFFH) of the data memory. The generalpurpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL). These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of the 4register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank. Caution It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for fetching instructions or as a stack area. R01UH0317EJ0004 Rev. 0.04 95 Feb. 22, 2013 00H PSW PSW
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 3 CPU ARCHITECTURE FFEFFH FFEF8H FFEF0H FFEE8H FFEE0H FFEFFH FFEF8H FFEF0H FFEE8H FFEE0H Register bank 0 Register bank 1 Register bank 2 Register bank 3 Register bank 0 Register bank 1 Register bank 2 Register bank 3 Figure 3-19. Configuration of General-Purpose Registers (a) Function name 16-bit processing 8-bit processing R01UH0317EJ0004 Rev. 0.04 96 Feb. 22, 2013 HL DE BC AX 15 0 7 0 (b) Absolute name 16-bit processing 8-bit processing RP3 RP2 RP1 RP0 15 0 7 0 H L D E B C A X R7 R6 R5 R4 R3 R2 R1 R0
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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19.2 Configuration of DMA Controlle
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34.2 64-pin products 1276 R5F10CLDx
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RL78/D1A User’s Manual: Hardware
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