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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 12 SERIAL ARRAY UNIT<br />

12.6.3 Data reception<br />

Data reception is an operation to receive data to the target for transfer (slave) after transmission of an address field.<br />

After all data are received to the slave, a stop condition is generated and the bus is released.<br />

Simplified I 2 C IIC11<br />

Target channel Channel 1 of SAU1<br />

Pins used SCL11, SDA11<br />

Interrupt<br />

INTIIC11<br />

Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)<br />

Error detection flag Overrun error detection flag (OVFmn) only<br />

Transfer data length 8 bits<br />

Transfer rate Max. fMCK/4 [Hz] (SDRmn[15:9] = 1 or more) fMCK: Operation clock frequency of target channel<br />

However, the following condition must be satisfied in each mode of I 2 C.<br />

Max. 400 kHz (first mode)<br />

Max. 100 kHz (standard mode)<br />

Data level Forward output (default: high level)<br />

Parity bit No parity bit<br />

Stop bit Appending 1 bit (ACK transmission)<br />

Data direction MSB first<br />

R01UH0317EJ0004 Rev. 0.04 660<br />

Feb. 22, 2013

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