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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)<br />

13.2 Configuration<br />

INTLTn<br />

INTLRn<br />

INTLSn<br />

LRxDn pin<br />

fCLK<br />

LIN0EN<br />

UFnID<br />

LIN1EN<br />

Comparison<br />

Figure 13-1. Block Diagram of Asynchronous Serial Interface LIN-UART<br />

UFnRX<br />

Receive shift<br />

register<br />

Filter<br />

Selector<br />

Automatic baud rate<br />

setting circuit<br />

Peripheral enable register 0 (PER0)<br />

Prescaler<br />

Reception unit<br />

Transmit/<br />

receive data<br />

comparison<br />

Reception<br />

controller<br />

Baud rate<br />

generator Note<br />

Internal bus<br />

UFnCTL1 UFnCTL0<br />

UFnBUCTL<br />

UFnBUF0 to<br />

UFnBUF8<br />

UF0BUF0<br />

UFnSTR<br />

UFnSTC<br />

Internal bus<br />

Transmission<br />

unit<br />

Transmission<br />

controller<br />

Baud rate<br />

generator Note<br />

UFnTX<br />

(UFnTXB)<br />

UFnWTX<br />

(UFnWTXB)<br />

Transmit shift<br />

register<br />

Selector<br />

LTxDn pin<br />

UFnOPT1 UFnOPT0 UFnOPT2<br />

Note For the configuration of the baud rate generator, see Figure 13-72 Configuration of Baud Rate Generator.<br />

Remark n = 0, 1<br />

R01UH0317EJ0004 Rev. 0.04 683<br />

Feb. 22, 2013

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