RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 24 VOLTAGE DETECTOR Supply voltage (VDD) Figure 24-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 0) (1/2) if a reset is not generated after releasing the mask, determine that a condition of VDD becomes VDD LVDH, clear LVIMD, and the MCU returns to normal operation. VLVDH VLVDL LVIMK flag (set by software) Operation status LVIF flag LVISEN flag (set by software) LVIOMSK flag LVIMD flag LVILV flag LVIRF flag LVD reset signal POR reset signal Internal reset signal INTLVI LVIIF flag RESET H Note 1 Cleared by software Normal operation Normal operation Save processing (Notes and Remark are listed on the next page.) Cleared by software Note 2 RESET Normal operation RESET Save processing Cleared by software Note 3 R01UH0317EJ0004 Rev. 0.04 1125 Feb. 22, 2013 W Cleared by software Time Cleared Cleared Note 3
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 24 VOLTAGE DETECTOR Notes 1. The LVIMK flag is set to “1” by reset signal generation. 2. After an interrupt is generated, perform the processing according to Figure 24-7 Processing Procedure After an Interrupt Is Generated in interrupt and reset mode. 3. After a reset is released, perform the processing according to Figure 24-8 Initial Setting of Interrupt and Reset Mode in interrupt and reset mode. Remark VPOR: POR power supply rise detection voltage VPDR: POR power supply fall detection voltage R01UH0317EJ0004 Rev. 0.04 1126 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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19.2 Configuration of DMA Controlle
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RL78/D1A User’s Manual: Hardware
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