RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 28 FLASH MEMORY An overview of the data flash memory is provided below. The data flash memory can be written to by using the flash memory programmer or an external device Programming is performed in 8-bit units Blocks can be deleted in 1 KB units The only access by CPU instructions is byte reading (1 clock cycle + wait 3 clock cycles) Because the data flash memory is an area exclusively used for data, it cannot be used to execute instructions (code fetching) Instructions can be executed from the code flash memory while rewriting the data flash memory (That is, back ground operation (BGO) is supported) Accessing the data flash memory is not possible while rewriting the code flash memory (during self programming) Because the data flash memory is stopped after a reset ends, the data flash control register (DFLCTL) must be set up in order to use the data flash memory Manipulating the DFLCTL register is not possible while rewriting the data flash memory Transition to the HALT/STOP status is not possible while rewriting the data flash memory 28.4.2 Register controlling data flash memory (1) Data flash control register (DFLCTL) This register is used to enable or disable accessing to the data flash. The DFLCTL register is set by a 1-bit or 8-bit memory manipulation instruction. Reset input sets this register to 00H. Figure 28-6. Format of Data Flash Control Register (DFLCTL) Address: F0090H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 DFLCTL 0 0 0 0 0 0 0 DFLEN DFLEN Data flash access control 0 Disables data flash access 1 Enables data flash access Caution Manipulating the DFLCTL register is not possible while rewriting the data flash memory. R01UH0317EJ0004 Rev. 0.04 1169 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 28 FLASH MEMORY 28.4.3 Procedure for accessing data flash memory The data flash memory is initially stopped after a reset ends and cannot be accessed (read or programmed). To access the memory, perform the following procedure: Write 1 to bit 0 (DFLEN) of the data flash control register (DFLCTL). Wait for the setup to finish. The time setup takes differs for each main clock mode. HS (High-speed main): 5 s After the wait, the data flash memory can be accessed. Cautions 1. Accessing the data flash memory is not possible during the setup time. 2. Before executing a STOP instruction during the setup time, temporarily clear DFLEN to 0. R01UH0317EJ0004 Rev. 0.04 1170 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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34.2 64-pin products 1276 R5F10CLDx
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34.4 100-pin products 1278 CHAPTER
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