RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 11 A/D CONVERTER Table 11-3. A/D Conversion Time Selection (4/4) (4) When there is stabilization wait time Low-voltage mode 1, 2 (hardware trigger wait mode) A/D Converter Mode Mode Conversion Number of Number of Stabilization Stabilization Wait + Conversion Time Selection Register 0 (ADM0) Clock (fAD) Stabilization Conversion Wait 2.7 V VDD 5.5 V FR2 FR1 FR0 LV1 LV0 Wait Cock Clock +Conversion fCLK = fCLK = fCLK = fCLK = fCLK = Time 1 MHz 4 MHz 8 MHz 16 MHz 32 MHz 0 0 0 1 0 Low- fCLK/64 2 fAD 19 fAD 1344/fCLK Setting Setting Setting Setting 42 s voltage (number of prohibited prohibited prohibited prohibited 0 0 1 1 fCLK/32 sampling 672/fCLK 42 s 21 s 0 1 0 fCLK/16 clock: 336/fCLK 42 s 21 s 0 1 1 fCLK/8 7 fAD) 168/fCLK 42 s 21 s 1 0 0 fCLK/6 126/fCLK 31.5 s 1 0 1 fCLK/5 105/fCLK 26.25 s 1 1 0 fCLK/4 84/fCLK 1 1 1 fCLK/2 42/fCLK 42 s Setting Setting Setting Setting prohibited prohibited prohibited prohibited 0 0 0 1 1 Low- fCLK/64 2 fAD 17 fAD 1216/fCLK Setting Setting Setting Setting 38 s voltage (number of prohibited prohibited prohibited prohibited 0 0 1 2 fCLK/32 sampling 608/fCLK 38 s 19 s 0 1 0 fCLK/16 clock: 304/fCLK 38 s 19 s 0 1 1 fCLK/8 5 fAD) 152/fCLK 38 s 19 s R01UH0317EJ0004 Rev. 0.04 517 Feb. 22, 2013 21 s 1 0 0 fCLK/6 114/fCLK 28.5 s 1 0 1 fCLK/5 96/fCLK 23.75 s 1 1 0 fCLK/4 76/fCLK 1 1 1 fCLK/2 19 s 38/fCLK 38 s Setting Setting Setting Setting prohibited prohibited prohibited prohibited Cautions 1. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the same data, while in the conversion stopped/conversion standby status (ADCS = 0). 2. The above conversion time does not include conversion start time. Conversion start time add in the first conversion. Select conversion time, taking clock frequency errors into consideration. 3. When hardware trigger wait mode, specify the conversion time, including the stabilization wait time from the hardware trigger detection. Remark fCLK: CPU/peripheral hardware clock frequency
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 11 A/D CONVERTER Figure 11-5. A/D Converter Sampling and A/D Conversion Timing (Example for Software Trigger Mode) ADCS Sampling timing INTAD ADCS ← 1 or ADS rewrite SAR clear Sampling Successive conversion Transfer to ADCR, INTAD generation Sampling Conversion time Conversion time (3) A/D converter mode register 1 (ADM1) This register is used to specify the A/D conversion trigger, conversion mode, and hardware trigger signal. Hardware trigger mode with ADTRG is added to be supported. ADTRG is allocated to P72 as alternate function. The ADM1 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Address: FFF32H After reset: 00H R/W R01UH0317EJ0004 Rev. 0.04 518 Feb. 22, 2013 SAR clear Figure 11-6. Format of A/D Converter Mode Register 1 (ADM1) Symbol 7 6 5 4 3 2 1 0 ADM1 ADTMD1 ADTMD0 ADSCM 0 0 0 ADTRS1 ADTRS0 ADTMD1 ADTMD0 Selection of the A/D conversion trigger mode 0 × Software trigger mode 1 0 Hardware trigger no-wait mode 1 1 Hardware trigger wait mode ADSCM Specification of the A/D conversion mode 0 Sequential conversion mode 1 One-shot conversion mode ADTRS1 ADTRS0 Selection of the hardware trigger signal 0 0 End of TAU 02 count or capture interrupt (INTTM02) 0 1 End of TAU 04 count or capture interrupt (INTTM04) 1 0 Hardware trigger from external pin (ADTRG) without noise filter 1 1 Hardware trigger from external pin (ADTRG) with noise filter (Caution and Remark are given on the next page.)
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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RL78/D1A User’s Manual: Hardware
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