RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)
13.7.3 ID parity check function
When the ID parity check select bit is set (UFnIPCS = 1) in automatic baud rate mode (UFnMD1, UFnMD0 = 11B), the
PID parity bits (P0, P1) are checked when the received PID is stored into the UFnID register. At that time, if either parity
bit includes an error, an ID parity error flag (UFnIPE) is set, a status interrupt request signal (INTLSn) is generated instead
of a reception complete interrupt request signal (INTLRn), and the PID is stored into the UFnID register.
INTLSn
UFnIPE flag
Figure 13-62. PID Parity Error Occurrence Example
LRxDn pin start ID0 ID1 ID2 ID3 ID4 ID5 P0 P1 stop
Error present
UFnID register PID
Remark n = 0, 1
Sets UFnCLIPE bit to 1
13.7.4 Automatic checksum function
When the automatic checksum enable bit is set (UFnACE = 1) in automatic baud rate mode (UFnMD1, UFnMD0 = 11B),
a checksum is automatically calculated. Enhanced checksum (calculation targets: PID and data) and classic checksum
(calculation target: only data) can be selected for each frame by using the enhanced checksum selection bit (UFnECS).
During response transmission, calculation is performed when data is transferred in 1-byte units from a buffer register to
a transmit shift register Note , and the calculation result is automatically added to the end of response transmission and
transmitted. A checksum is not required to be set to a buffer by using software.
During response reception, calculation is performed when data is stored into a buffer register in 1-byte units Note , and the
stored data and calculation result are automatically compared when the received checksum is stored into a buffer. A
reception complete interrupt request signal (INTLRn) is generated when the comparison result is correct. If the
comparison result is illegal, however, a status interrupt request signal (INTLSn) is generated instead of a reception
complete interrupt request signal (INTLRn), a checksum error flag (UFnCSE) is set, and the checksum is stored into the
UFnRX register.
Note With enhanced checksum, the value of the UFnID register can be set initial value of calculate when transfer start.
Remark n = 0, 1
R01UH0317EJ0004 Rev. 0.04 762
Feb. 22, 2013
Clear