RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT 12.5.1 Master transmission Master transmission is that the RL78/D1A outputs a transfer clock and transmits data to another device. 3-Wire Serial I/O CSI00 CSI01 CSI10 Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 0 of SAU1 Pins used SCK00, SO00 SCK01, SO01 SCK10, SO10 Interrupt Error detection flag None Transfer data length 7 to 16 bits INTCSI00 INTCSI01 INTCSI10 Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected. Transfer rate Max. fCLK/4 [Hz], Min. fCLK/(2 2 11 128) [Hz] Note fCLK: System clock frequency Data phase Selectable by DAPmn bit DAPmn = 0: Data output starts from the start of the operation of the serial clock. DAPmn = 1: Data output starts half a clock before the start of the serial clock operation. Clock phase Selectable by CKPmn bit CKPmn = 0: Forward CKPmn = 1: Reverse Data direction MSB or LSB first Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical specifications (see CHAPTER 32 ELECTRICAL SPECIFICATIONS (J GRADE PRODUCT) (TARGET) and CHAPTER 33 ELECTRICAL SPECIFICATIONS (L GRADE PRODUCT) (TARGET). R01UH0317EJ0004 Rev. 0.04 591 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 12 SERIAL ARRAY UNIT (1) Register setting Figure 12-26. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O (CSI00, CSI01, CSI10) (1/2) (a) Serial output register m (SOm) … Sets only the bits of the target channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOm 0 0 0 0 0 0 CKOm1 0/1 CKOm0 0/1 R01UH0317EJ0004 Rev. 0.04 592 Feb. 22, 2013 0 0 0 0 0 0 SOm1 0/1 SOm0 0/1 Communication starts when these bits are 1 if the data phase is forward (CKPmn = 0). If the phase is reversed (CKPmn = 1), communication starts when these bits are 0. (b) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOEm 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOEm1 0/1 (c) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSm 0 0 0 0 0 0 0 (d) Serial mode register mn (SMRmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SMRmn CKSmn 0/1 CCSmn 0 0 0 0 0 0 0 STSmn 0 0 0 0 0 0 1 0 0 0 0 0 MDmn2 0 SSm1 0/1 MDmn1 0 SOEm0 0/1 SSm0 0/1 MDmn0 0/1 Interrupt sources of channel n 0: Transfer end interrupt 1: Buffer empty interrupt (e) Serial communication operation setting register mn (SCRmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SCRmn TXEmn 1 RXEmn 0 DAPmn 0/1 CKPmn 0/1 (f) Serial data register mn (SDRmn) 0 0 0 0 DIRmn 0/1 0 SLCmn1 0 SLCmn0 0 DLSmn3 0/1 DLSmn2 0/1 DLSmn1 0/1 (i) When operation is stopped (SEmn = 0) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDRmn Baud rate setting 0 Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), p: CSI number (p = 00, 01, 10) : Setting is fixed in the CSI master transmission mode, : Setting disabled (set to the initial value) 0/1: Set to 0 or 1 depending on the usage of the user 0 0 0 0 0 0 0 DLSmn0 0/1 0
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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RL78/D1A User’s Manual: Hardware
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