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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 6 TIMER ARRAY UNIT<br />

(d) Start timing in one-count mode<br />

Writing 1 to TSmn sets TEmn = 1.<br />

Enters the start trigger input wait status, and TCRmn holds the initial value.<br />

On start trigger detection, the “TDRmn value” is loaded to TCRmn and count starts.<br />

Figure 6-18. Start Timing (In One-count Mode)<br />

fCLK<br />

TSmn (write)<br />

TEmn<br />

TImn edge detection signal<br />

Count clock Note<br />

TSmn (write) hold signal<br />

Start trigger detection signal<br />

TCRmn<br />

<br />

<br />

Initial value<br />

TDRmn value<br />

Start trigger input wait status<br />

Note When the one-count mode is set, the operation clock (fMCK) is selected as count clock (CCSmn = 0).<br />

Caution An input signal sampling error is generated since operation starts upon start trigger detection<br />

(The error is one count clock when TImn is used).<br />

Remark m: Unit number (m = 0 to 2)<br />

n: Channel number (n = 0 to 7)<br />

R01UH0317EJ0004 Rev. 0.04 342<br />

Feb. 22, 2013

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