RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 31 INSTRUCTION SET Instruction Mnemonic Group Operands Bytes Stack manipulate Unconditio nal branch Conditional branch PUSH POP MOVW Table 31-5. Operation List (16/17) Clocks Operation Flag Note 1 Note 2 Z AC CY PSW 2 1 (SP 1) PSW, (SP 2) 00H, SP SP 2 rp 1 1 (SP 1) rpH, (SP 2) rpL, SP SP 2 PSW 2 3 PSW (SP + 1), SP SP + 2 R R R rp 1 1 rpL (SP), rpH (SP + 1), SP SP + 2 SP, #word 4 1 SP word SP, AX 2 1 SP AX AX, SP 2 1 AX SP HL, SP 3 1 HL SP BC, SP 3 1 BC SP DE, SP 3 1 DE SP ADDW SP, #byte 2 1 SP SP + byte SUBW SP, #byte 2 1 SP SP byte BR AX 2 3 PC CS, AX $addr20 2 3 PC PC + 2 + jdisp8 $!addr20 3 3 PC PC + 3 + jdisp16 !addr16 3 3 PC 0000, addr16 !!addr20 4 3 PC addr20 Note 3 BC $addr20 2 2/4 Note 3 BNC $addr20 2 2/4 Note 3 BZ $addr20 2 2/4 Note 3 BNZ $addr20 2 2/4 Note 3 BH $addr20 3 2/4 Note 3 BNH $addr20 3 2/4 BT Note 3 saddr.bit, $addr20 4 3/5 Note 3 sfr.bit, $addr20 4 3/5 Note 3 A.bit, $addr20 3 3/5 Note 3 PSW.bit, $addr20 4 3/5 Note 3 [HL].bit, $addr20 3 3/5 ES:[HL].bit, $addr20 Note 3 4 4/6 PC PC + 2 + jdisp8 if CY = 1 PC PC + 2 + jdisp8 if CY = 0 PC PC + 2 + jdisp8 if Z = 1 PC PC + 2 + jdisp8 if Z = 0 PC PC+3+jdisp8 if (Z CY)=0 PC PC+3+jdisp8 if (Z CY)=1 PC PC + 4 + jdisp8 if (saddr).bit = 1 PC PC + 4 + jdisp8 if sfr.bit = 1 PC PC + 3 + jdisp8 if A.bit = 1 PC PC + 4 + jdisp8 if PSW.bit = 1 6/7 PC PC + 3 + jdisp8 if (HL).bit = 1 7/8 PC PC + 4 + jdisp8 if (ES, HL).bit = 1 Notes 1. When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data access. 2. When the program memory area is accessed. 3. This indicates the number of clocks “when condition is not met/when condition is met”. Remark This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum. R01UH0317EJ0004 Rev. 0.04 1209 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 31 INSTRUCTION SET Instruction Mnemonic Group Operands Bytes Condition al branch Conditional skip CPU control BF BTCLR saddr.bit, $addr20 4 Note 3 3/5 sfr.bit, $addr20 4 Note 3 3/5 A.bit, $addr20 3 Note 3 3/5 PSW.bit, $addr20 4 Note 3 3/5 [HL].bit, $addr20 3 Note 3 3/5 ES:[HL].bit, $addr20 4 Note 3 4/6 saddr.bit, $addr20 4 Note 3 3/5 Note 3 sfr.bit, $addr20 4 3/5 Note 3 A.bit, $addr20 3 3/5 Note 3 PSW.bit, $addr20 4 3/5 Note 3 [HL].bit, $addr20 3 3/5 Note 3 ES:[HL].bit, $addr20 4 4/6 Table 31-5. Operation List (17/17) Clocks Operation Flag Note 1 Note 2 Z AC CY PC PC + 4 + jdisp8 if (saddr).bit = 0 PC PC + 4 + jdisp8 if sfr.bit = 0 PC PC + 3 + jdisp8 if A.bit = 0 PC PC + 4 + jdisp8 if PSW.bit = 0 6/7 PC PC + 3 + jdisp8 if (HL).bit = 0 7/8 PC PC + 4 + jdisp8 if (ES, HL).bit = 0 PC PC + 4 + jdisp8 if (saddr).bit = 1 then reset (saddr).bit PC PC + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit PC PC + 3 + jdisp8 if A.bit = 1 then reset A.bit PC PC + 4 + jdisp8 if PSW.bit = 1 then reset PSW.bit PC PC + 3 + jdisp8 if (HL).bit = 1 then reset (HL).bit PC PC + 4 + jdisp8 if (ES, HL).bit = 1 then reset (ES, HL).bit SKC 2 1 Next instruction skip if CY = 1 SKNC 2 1 Next instruction skip if CY = 0 SKZ 2 1 Next instruction skip if Z = 1 SKNZ 2 1 Next instruction skip if Z = 0 SKH 2 1 Next instruction skip if (Z CY) = 0 SKNH 2 1 Next instruction skip if (Z CY) = 1 SEL Note4 RBn 2 1 RBS[1:0] n NOP 1 1 No Operation EI 3 4 IE 1(Enable Interrupt) DI 3 4 IE 0(Disable Interrupt) HALT 2 3 Set HALT Mode STOP 2 3 Set STOP Mode Notes 1. When the internal RAM area, SFR area, or extended SFR area is accessed, or for an instruction with no data access. 2. When the program memory area is accessed. 3. This indicates the number of clocks “when condition is not met/when condition is met”. 4. n indicates the number of register banks (n = 0 to 3) Remark This number of clocks is for when the program is in the internal ROM (flash memory) area. When fetching an instruction from the internal RAM area, the number of clocks is twice the number of clocks plus 3, maximum. R01UH0317EJ0004 Rev. 0.04 1210 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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RL78/D1A User’s Manual: Hardware
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