RL78/D1A User's Manual: Hardware - Renesas

Under development
Preliminary document
Specifications in this document are tentative and subject to change.
RL78/D1A CHAPTER 3 CPU ARCHITECTURE
Data memory
space
Program
memory
space
FFFFFH
FFF00H
FFEFFH
FFEE0H
FFEDFH
FBF00H
FBEFFH
F3000H
F2FFFH
F1000H
F0FFFH
F0800H
F07FFH
F0000H
EFFFFH
40000H
3FFFFH
00000H
Figure 3-7. Memory Map (R5F10DMJxFB, R5F10TPJxFB, R5F10DPJxFB)
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
Notes 1, 2
RAM
16 KB
Mirror
35.75 KB
Data flash memory
8 KB
Reserved
Special function register (2nd SFR)
2 KB
Reserved
Code flash memory
256 KB
3FFFFH
020CEH
020CDH
020C4H
020C3H
020C0H
020BFH
02080H
0207FH
02000H
01FFFH
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
00080H
0007FH
00000H
Program area
On-chip debug security
Note 3
ID setting area
10 bytes
Note 3
Option byte area
4 bytes
CALLT table area
64 bytes
Vector table area
128 bytes
Program area
On-chip debug security
Note 3
ID setting area
10 bytes
Note 3
Option byte area
4 bytes
CALLT table area
64 bytes
Vector table area
128 bytes
03FFFH
Boot cluster 1
Boot cluster 0Note 4
Notes 1. Use of part of this area is prohibited by libraries, when using the self-programming function and data flash
function.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
IDs to 000C4H to 000CDH.
When boot swap is used: Set the option bytes to 000C0H to 000C3H and 020C0H to 020C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 020C4H to 020CDH.
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 28.6 Security Setting).
Caution When executing instructions from the RAM area while RAM parity error resets are enabled (RPERDIS
= 0), be sure to initialize the used RAM area + 10 bytes.
R01UH0317EJ0004 Rev. 0.04 75
Feb. 22, 2013