RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 6 TIMER ARRAY UNIT (4) Timer status register mn (TSRmn) TSRmn indicates the overflow status of the counter of channel n. TSRmn is valid only in the capture mode (MDmn3 to MDmn1 = 010B) and capture & one-count mode (MDmn3 to MDmn1 = 110B). It will not be set in any other mode. See Table 6-3 for the operation of the OVF bit in each operation mode and set/clear conditions. TSRmn can be read by a 16-bit memory manipulation instruction. The lower 8 bits of TSRmn can be set with an 8-bit memory manipulation instruction with TSRmnL. Reset signal generation clears this register to 0000H. Figure 6-12. Format of Timer Status Register mn (TSRmn) Address: F01A0H, F01A1H (TSR00) to F01AEH, F01AFH (TSR07), After reset: 0000H R F01E0H, F01E1H (TSR10) to F01EEH, F01EFH (TSR17), F0220H, F0221H (TSR20) to F022EH, F022FH (TSR27), Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSRmn 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF OVF Counter overflow status of channel n 0 Overflow does not occur. 1 Overflow occurs. When OVF = 1, this flag is cleared (OVF = 0) when the next value is captured without overflow. Remark m: Unit number (m = 0 to 2) n: Channel number (n = 0 to 7) Table 6-3. OVF Bit Operation and Set/Clear Conditions in Each Operation Mode Timer Operation Mode OVF Set/Clear Conditions Capture mode clear When no overflow has occurred upon capturing Capture & one-count mode set When an overflow has occurred upon capturing Interval timer mode clear Event counter mode (Use prohibited, not set/cleared) One-count mode set Remark The OVF bit does not change immediately after the counter has overflowed, but changes upon the subsequent capture. R01UH0317EJ0004 Rev. 0.04 335 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 6 TIMER ARRAY UNIT (5) Timer channel enable status register m (TEm) TEm is used to enable or stop the timer operation of each channel. When a bit of timer channel start register m (TSm) is set to 1, the corresponding bit of this register is set to 1. When a bit of timer channel stop register m (TTm) is set to 1, the corresponding bit of this register is cleared to 0. TEm can be read by a 16-bit memory manipulation instruction. The lower 8 bits of TEm can be read with a 1-bit or 8-bit memory manipulation instruction with TEmL. Reset signal generation clears this register to 0000H. Figure 6-13. Format of Timer Channel Enable Status Register m (TEm) Address: F01B0H, F01B1H (TE0), F01F0H, F01F1H (TE1), After reset: 0000H R F0230H, F0231H (TE2) Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEm 0 0 0 0 0 0 0 0 TEm7 TEm6 TEm5 TEm4 TEm3 TEm2 TEm1 TEm0 TE mn 0 Operation is stopped. 1 Operation is enabled. Caution Be sure to clear bits 15 to 8 of TEm to 0. Remark m: Unit number (m = 0 to 2) n: Channel number (n = 0 to 7) Indication of operation enable/stop status of channel n R01UH0317EJ0004 Rev. 0.04 336 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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