RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 5 CLOCK GENERATOR (13) Peripheral Clock select register (PCKSEL) Figure 5-15. Format of Peripheral Clock select register (PCKSEL) Address: F00F2H After reset: 00H @R/W (Note: Bits 1,2 and 7 are Read Only) Symbol PCKSEL 0 CAN MCKE1 CAN MCK1 CAN MCKE0 CAN MCK0 0 0 SGCLK SEL CANMCKE1 Supply/stop control of clock (bus & operation) of aFCAN unit1 0 Stops supplying clock (bus & operation) of aFCAN unit1 1 Supplies clock (bus & operation) of aFCAN unit1 CANMCK1 Input clock (operation) supply selection of aFCAN unit1 0 fMAIN is supplied 1 fMP is supplied CANMCKE0 Supplies/stops control of clock (bus & operation) of aFCAN unit0 0 Stops supplying clock (bus & operation) of aFCAN unit0 1 Supplies clock (bus & operation) of aFCAN unit0 CANMCK0 Input clock (operation) supply selection of aFCAN unit0 0 fMAIN is supplied 1 fMP is supplied SGCLKSEL Clock (operation) source supply selection of Sound Generator 0 fCLK is supplied 1 fCLK/2 is supplied R01UH0317EJ0004 Rev. 0.04 289 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 5 CLOCK GENERATOR 5.4 Clock monitor (CLM) The clock monitor uses the low-speed on-chip oscillator to sample the main system clock (fMAIN) and PLL clock(fPLL). If oscillation of the main system clock stops, a reset request signal (RESFCLM) is generated. If the PLL clock stops, an interrupt request signal (INTCLM) is generated. Up to 4 clocks of fIL is necessary to detect stop of Main OSC/PLL. After detection, reset/interrupt request will immediately occurs. When CLM macro monitors PLL clock (fPLL) and PLL clock stops, clock through is selected (original clock to PLL input), but the FF/flag of SELPLL/SELPLLS itself is not cleared, so it is necessary to reset chip before select PLL clock again. Table 5-4: Clock Monitor Operation Conditions Condition Optionbyte Clock monitor operation fCLK=fSUB - Stop fIL Stop - Stop STOP mode - Stop During oscillation fCLK=fMP/2 stabilization after MCM0 setting - Stop CLKMB=1 Stop N fIL Operation Other than above CLKMB=0 Operation As described in above table, fIL must be operated to activate CLM. fIL operation is controled by the combination of below factor. - WDSTBYON option byte - WDTON option byte - WUTMMCK0 bit - Chip status (RUN/HALT/STOP/SNOOZE) Please refer to the description of “Clock tree” for detail. R01UH0317EJ0004 Rev. 0.04 290 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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RL78/D1A User’s Manual: Hardware
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