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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 14 CAN CONTROLLER<br />

END<br />

Figure 14-78. Reception via Interrupt (Using C0RGPT Register)<br />

Yes<br />

START<br />

Generation of receive<br />

completion interrupt<br />

Read C0RGPT register<br />

ROVF = 1?<br />

Yes<br />

Clear ROVF bit<br />

RHPM = 1?<br />

Clear DN bit<br />

DN = 0<br />

AND<br />

MUC = 0 Note<br />

Yes<br />

No<br />

Read C0MDATAxm, C0MDLCm,<br />

C0MIDLm, C0MIDHm registers<br />

Note Check the MUC and DN bits using one read access.<br />

R01UH0317EJ0004 Rev. 0.04 934<br />

Feb. 22, 2013<br />

No<br />

No<br />

Correct data is read Illegal data is read<br />

Remarks 1. Also check the MBON flag at the beginning and at the end of the interrupt routine, in order to<br />

check the access to the message buffers as well as reception history list registers, in case a<br />

pending sleep mode had been executed. If MBON is detected to be cleared at any check, the<br />

actions and results of the processing have to be discarded and processed again, after MBON is<br />

set again.<br />

It is recommended to cancel any sleep mode requests, before processing RX interrupts.<br />

2. If ROVF was set once, the receive history list is inconsistent. Consider to scan all configured<br />

receive buffers for receptions.

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