RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 18 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Operation clock Figure 18-8. Timing Diagram of Multiply-Accumulation (Unsigned) Operation (2 3 + 3 = 9 32767 2 + 4294901762 = 0 (over flow generated)) 00H 40H 44H MDCH 0000H 0000H 0000H FFFFH 0000H MDCL 0000H 0003H 0009H , 0002H 0000H MDAL 0000H 0002H 7FFFH MDAH MDBH MDBL INTMD MACOF MACSF L 0000H 0003H 0002H 0000H 0000H 0000H 0006H R01UH0317EJ0004 Rev. 0.04 1021 Feb. 22, 2013 0000H FFFEH
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 18 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 18.4.4 Multiply-accumulation (signed) operation • Initial setting Set the multiplication/division control register (MDUC) to 48H. Set the initial accumulated value of higher 16 bits to multiplication/division data register C (H) (MDCH). ( If the accumulated value in the MDCH register is negative, the MACSF bit is set to 1.) Set the initial accumulated value of lower 16 bits to multiplication/division data register C (L) (MDCL). Set the multiplicand to multiplication/division data register A (L) (MDAL). Set the multiplier to multiplication/division data register A (H) (MDAH). (There is no preference in the order of executing steps , , and . Multiplication operation is automatically started when the multiplier is set to the MDAH register, respectively.) • During operation processing The multiplication operation finishes in one clock cycle. (The multiplication result is stored in multiplication/division data register B (L) (MDBL) and multiplication/division data register B (H) (MDBH).) After , the multiply-accumulation operation finishes in one additional clock cycle. (There is a wait of at least two clock cycles after specifying the initial settings is finished ().) • Operation end If the accumulated value stored in the MDCL and MDCH registers is positive, the MACSF bit is cleared to 0. Read the accumulated value (lower 16 bits) from the MDCL register. Read the accumulated value (higher 16 bits) from the MDCH register. (There is no preference in the order of executing steps and .) ( If the result of the multiply-accumulation operation causes an overflow, the MACOF bit is set to 1, INTMD signal is occurred.) • Next operation The next time multiplication, division or multiply-accumulation is performed, start with the initial settings of each step. Caution The data is in the two's complement format in multiply-accumulation (signed) operation. Remark Steps to correspond to to in Figure 18-9. R01UH0317EJ0004 Rev. 0.04 1022 Feb. 22, 2013
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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19.2 Configuration of DMA Controlle
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