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RL78/D1A User's Manual: Hardware - Renesas

RL78/D1A User's Manual: Hardware - Renesas

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Under development<br />

Preliminary document<br />

Specifications in this document are tentative and subject to change.<br />

<strong>RL78</strong>/<strong>D1A</strong> CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE LIN-UART (UARTF)<br />

LIN-UART consists of the following hardware units.<br />

Table 13-1. Configuration of LIN-UARTn<br />

Item Configuration<br />

Registers Peripheral enable register 0 (PER0)<br />

LIN-UARTn control registers 0, 1 (UFnCTL0, UFnCTL1)<br />

LIN-UARTn option registers 0 to 2 (UFnOPT0 to UFnOPT2)<br />

LIN-UARTn status register (UFnSTR)<br />

LIN-UARTn status clear register (UFnSTC)<br />

LIN-UARTn receive shift register<br />

LIN-UARTn receive data register (UFnRX)<br />

LIN-UARTn 8-bit receive data register (UFnRXB)<br />

LIN-UARTn transmit shift register<br />

LIN-UARTn transmit data register (UFnTX)<br />

LIN-UARTn 8-bit transmit data register (UFnTXB)<br />

LIN-UARTn wait transmit data register (UFnWTX)<br />

LIN-UARTn 8-bit wait transmit data register (UFnWTXB)<br />

LIN-UARTn ID setting register (UFnID)<br />

LIN-UARTn buffer registers 0 to 8 (UFnBUF0 to UFnBUF8)<br />

LIN-UARTn buffer control register (UFnBUCTL)<br />

Serial communication pin select register 0, 1 (STSEL0, 1)<br />

Port mode registers 1, 7, 13 (PM1, PM7, PM13)<br />

Remark n = 0, 1<br />

R01UH0317EJ0004 Rev. 0.04 684<br />

Feb. 22, 2013

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