RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-82. Example of Basic Timing of Operation as Multiple PWM Output Function (Output Two Types of PWMs) Master channel Slave channel 1 Slave channel 2 TSmn TEmn TCRmn TDRmn TOmn INTTMmn TSmp TEmp TCRmp TDRmp TOmp INTTMmp TSmq TEmq TCRmq TDRmq TOmq INTTMmq FFFFH 0000H FFFFH 0000H FFFFH 0000H e c c a b a+1 a+1 b+1 c d e f a+1 a+1 b+1 e f f Remark m: Unit number (m = 0 to 2), n: Channel number, p, q: Slave channel number 1, 2 (n RL78/D1A CHAPTER 6 TIMER ARRAY UNIT Figure 6-83. Example of Set Contents of Registers When Multiple PWM Output Function (Master Channel) Is Used (1/2) (a) Timer mode register mn (TMRmn) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TMRmn CKSmn1 CKSmn0 1/0 1/0 0 CCSmn 0 MAS TERmn 1 STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 0 0 0 R01UH0317EJ0004 Rev. 0.04 450 Feb. 22, 2013 0 0 0 0 MDmn3 MDmn2 MDmn1 MDmn0 Operation mode of channel n 000B: Interval timer 0 0 Setting of operation when counting is started 1: Generates INTTMmn when counting is started. Selection of TImn pin input edge 00B: Sets 00B because these are not used. Start trigger selection 000B: Selects only software start. Slave/master selection 1: Channel 1 is set as master channel. Count clock selection 0: Selects operation clock. Operation clock selection 00B: Selects CKm0 as operation clock of channel n. 01B: Selects CKm1 as operation clock of channel n. 10B: Selects CKm2 as operation clock of channel n. 11B: Selects CKm3 as operation clock of channel n. (b) Timer output register m (TOm) Bit n 0: Outputs 0 from TOmn. 0 TOm TOmn (c) Timer output enable register m (TOEm) Bit n 0: Stops the TOmn output operation by counting operation. 0 TOEm TOEmn Remark m: Unit number (m = 0 to 2) n: Channel number (n = 0 to 7) 0 1
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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12.5.3 Master transmission/receptio
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19.2 Configuration of DMA Controlle
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