RL78/D1A User's Manual: Hardware - Renesas

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Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 17 SOUND GENERATOR (8) Sound generator and PCL pin select register (SGSEL) This register is used for alternate switch of sound generator and PCL output pins. SGOA output can be stopped when it is not used if SGSEL_2 is set to “1”. Address: FFF3F After reset: 00H R/W Figure 17-4. Format of SGSEL Register Symbol 7 6 5 4 3 2 1 0 SGSEL 0 0 0 0 PCLSEL SGSEL2 SGSEL1 SGSEL0 SGSEL2 SGSEL1 SGSEL0 Pin select of sound generator outputs SGO/SGOF SGOA 0 0 0 P73 P72 0 0 1 P93 P92 0 1 0 P135 P134 0 1 1 Setting prohibit 1 0 0 P73 1 0 1 P93 1 1 0 P135 1 1 1 Setting prohibit No port is selected (output disabled) R01UH0317EJ0004 Rev. 0.04 1005 Feb. 22, 2013
Under development Preliminary document Specifications in this document are tentative and subject to change. RL78/D1A CHAPTER 17 SOUND GENERATOR 17.3 Sound Generator Operation This section explains the details of the Sound Generator. 17.3.1 Generating the tone The tone signal is generated by the compare match signal of the SG0FH counter value with the value of the SG0FH buffer, followed by a by-two-divider. At each compare match, the counter is reset to zero. Remember that the SG0FH counter is clocked by the output of the SG0FL counter. (1) Updating the frequency buffer values The values of the frequency buffers can be changed by writing to the associated frequency registers SG0FL and SG0FH. Changing the value of the SG0FL (equivalent to SG0F[15:0]) register would also yield a change of the PWM frequency, i.e. the sound volume. Therefore it is obligatory to write the correct PWM value to SG0PWM before a new SG0FL value is copied to the frequency buffers. The following figure shows an example (not to scale). SG0CLK SG0FH Write SG0PWM SG0FH buffer SG0FH compare match SG0FH counter 003B H Figure 17-5. Update Timing of the Frequency Buffers 038 H 003B H 039 H 03A H If SG0FL is set to 01AEH and a 193 Hz tone is generated, as in the above example, the time span between writing to the SG0PWM register and updating the buffer can be up to 5.17 ms. R01UH0317EJ0004 Rev. 0.04 1006 Feb. 22, 2013 0027 H 03B H 000 H 0027 H 001 H
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User’s Manual 16 RL78/D1A 16-Bit
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NOTES FOR CMOS DEVICES (1) VOLTAGE
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Conventions Data significance: High
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CONTENTS CHAPTER 1 OUTLINE.........
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3.4.4 Short direct addressing .....
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6.8 Operation of Plural Channels of
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RL78/D1A User’s Manual: Hardware
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